Abstract: A memory device has at least one pair of memory cell blocks, a spare row decoder, a data exchange control signal generator and a data exchange unit. When a defective memory cell in a first memory cell block is repaired with a spare memory cell in a second memory cell block that neighbors (or is adjacent) the first memory cell block, the data topology of the memory cell of the first memory cell may be matched to the memory cell of the second memory cell block.

Abstract: A memory device has at least one pair of memory cell blocks, a spare row decoder, a data exchange control signal generator and a data exchange unit. When a defective memory cell in a first memory cell block is repaired with a spare memory cell in a second memory cell block that neighbors (or is adjacent) the first memory cell block, the data topology of the memory cell of the first memory cell may be matched to the memory cell of the second memory cell block.

Abstract: Provided is a semiconductor memory device having an output driver for high frequency operation. In the output driver of the semiconductor memory device, a first NMOS transistor and a second NMOS transistor are connected in series, the drain of the first NMOS transistor is connected to an output pad, and the source of the second NMOS transistor is connected to a ground voltage. In addition, a first internal voltage is applied to the gate of the first NMOS transistor, a second internal voltage is applied to a gate of the second NMOS transistor, and a voltage level of the second internal voltage is lower than the voltage level of an external supply voltage. The second internal voltage is generated directly from an internal voltage generating circuit of the semiconductor memory device or is externally applied. The voltage level of the second internal voltage is different from the level of an operating voltage of the semiconductor memory device.

Abstract: Clock generation circuits for an integrated circuit device are provided including a temperature sensor circuit, the temperatures sensor circuit including a calibration circuit responsive to a temperature coding signal and a temperature sensor. The temperature sensor circuit has a first or test mode state in which a temperature output signal of the temperature sensor circuit is based on a temperature sensor output control signal and a second or normal operating mode state in which the temperature output signal is based on the temperature sensor and the calibration circuit. A clock period controller circuit includes a calibration circuit responsive to a period coding signal. The clock period controller circuit generates a period control signal based on the temperature output signal and the calibration circuit of the clock period controller circuit. A clock generator circuit generates a clock signal based on the period control signal.

Abstract: Provided is a semiconductor memory device having an output driver for high frequency operation. In the output driver of the semiconductor memory device, a first NMOS transistor and a second NMOS transistor are connected in series, the drain of the first NMOS transistor is connected to an output pad, and the source of the second NMOS transistor is connected to a ground voltage. In addition, a first internal voltage is applied to the gate of the first NMOS transistor, a second internal voltage is applied to a gate of the second NMOS transistor, and a voltage level of the second internal voltage is lower than the voltage level of an external supply voltage. The second internal voltage is generated directly from an internal voltage generating circuit of the semiconductor memory device or is externally applied. The voltage level of the second internal voltage is different from the level of an operating voltage of the semiconductor memory device.

Abstract: A semiconductor memory device secures a margin of data setup time and hold time of a data terminal and includes a delay locked loop, an output replica, an output driver, and an output multiplexer. The delay locked loop compares phases of external and feedback clock signals, and generates internal and delayed internal clock signals. The output replica receives memory cell data, generates the feedback control signal and controls load of a line of the feedback control signal to generate the feedback clock signal, responsive to current control signals for controlling current of the data terminal. The output multiplexer delays the memory cell data by a predetermined time in synchronization with the internal clock signal and responsive to the current control signals. The output driver is driven by the current control signals and the delayed memory cell data, and determines voltage level of the data terminal.

Abstract: A ball grid array (BGA) package provides a constant internal voltage via an auxiliary routing configuration of a printed circuit board (PCB). The BGA package includes a substrate having an opening, a plurality of pads attached to an upper surface of the substrate, a semiconductor chip which has a plurality of bonding pads and which is attached to a lower surface of the substrate, an internal connection mechanism for connecting at least one of the bonding pads to at least one of the plurality of pads via the opening, and a filling material for filling the opening to protect the bonding pads and the internal connection mechanism. At least one of the plurality of bonding pads is electrically connected to at least one other of the plurality of bonding pads via an auxiliary routing configuration within the substrate.

Abstract: Clock generation circuits for an integrated circuit device are provided including a temperature sensor circuit, the temperatures sensor circuit including a calibration circuit responsive to a temperature coding signal and a temperature sensor. The temperature sensor circuit has a first or test mode state in which a temperature output signal of the temperature sensor circuit is based on a temperature sensor output control signal and a second or normal operating mode state in which the temperature output signal is based on the temperature sensor and the calibration circuit. A clock period controller circuit includes a calibration circuit responsive to a period coding signal. The clock period controller circuit generates a period control signal based on the temperature output signal and the calibration circuit of the clock period controller circuit. A clock generator circuit generates a clock signal based on the period control signal.

Abstract: Reference voltage regulators and methods for integrated circuit output driver systems generate an initial supplementary current for the integrated circuit output driver system at the reference voltage for a predetermined time period in response to an output enable signal. Preferably, sufficient initial supplementary current is generated to compensate for an initial drop in the reference voltage that is generated by a reference voltage generator upon initial activation of the output driver system. Reference voltage generators according to embodiments of the invention may be included in an integrated circuit output driver system that is responsive to a reference voltage and to an output enable signal, and that varies in current drive capability in response to a current drive control signal. These embodiments of reference voltage regulators include a reference voltage generator that generates the reference voltage for the integrated circuit output driver system.

Abstract: A semiconductor memory device secures a margin of data setup time and hold time of a data terminal and includes a delay locked loop, an output replica, an output driver, and an output multiplexer. The delay locked loop compares phases of external and feedback clock signals, and generates internal and delayed internal clock signals. The output replica receives memory cell data, generates the feedback control signal and controls load of a line of the feedback control signal to generate the feedback clock signal, responsive to current control signals for controlling current of the data terminal. The output multiplexer delays the memory cell data by a predetermined time in synchronization with the internal clock signal and responsive to the current control signals. The output driver is driven by the current control signals and the delayed memory cell data, and determines voltage level of the data terminal.

Abstract: A ball grid array (BGA) package provides a constant internal voltage via an auxiliary routing configuration of a printed circuit board (PCB). The BGA package includes a substrate having an opening, a plurality of pads attached to an upper surface of the substrate, a semiconductor chip which has a plurality of bonding pads and which is attached to a lower surface of the substrate, an internal connection mechanism for connecting at least one of the bonding pads to at least one of the plurality of pads via the opening, and a filling material for filling the opening to protect the bonding pads and the internal connection mechanism. At least one of the plurality of bonding pads is electrically connected to at least one other of the plurality of bonding pads via an auxiliary routing configuration within the substrate.

Abstract: A dynamic random access memory device and a &mgr;BGA package for the device use multiple pads for a reference voltage. The device includes n input receivers, n data input pads, and x reference voltage pads. Each input receiver operates synchronously with a clock signal and includes a differential amplifying unit that generates an output data signal according to a voltage difference between an input data signal and a reference voltage. The n data input pads respectively connect to the n input receivers and transfer the input data signals to the input receivers. The n input receivers are divided into x groups according to their positions, and the x reference voltage input pads respectively connect to the x groups of input receivers for commonly applying the reference voltage to the input receivers in the respective groups. Each reference voltage input pad can connect to its group of input receivers through one or multiple common lines. The package includes a first ball that receives the reference voltage.

Abstract: A variable loading circuit for controlling signal transmission on a signal line in an integrated circuit includes a capacitor. A loading control circuit is responsive to a control signal to variably couple the signal line and a signal node through the capacitor and thereby vary signal transmission time on the signal line. In embodiments of the present invention, the loading control circuit includes a series combination of a fuse and one or more switches. The one or more switches are responsive to respective control signals to variably couple the signal line to the signal node through the fuse and the capacitor. The variable loading circuits can be used to reduce skew among signals in systems where signal timing is critical. Related methods are also described.

Abstract: Integrated circuit memory devices include one or more input receivers that have a reference voltage input terminal. A conductor electrically couples the reference voltage input terminals to a reference voltage, and a capacitor is connected between the conductor and a first ground voltage. Preferably, the location of the connection between the capacitor and the conductor is selected in accordance with the electrical characteristics of the input receivers. Accordingly, the capacitor may reduce fluctuations or noise in the reference voltage applied to the reference voltage input terminals of the input receivers. The fluctuations or noise in the reference voltage may cause the input characteristics and/or the set-up and hold times of the input receivers to vary with respect to one another. A reduction in fluctuations or noise in the reference voltage may result in more consistent input characteristics among the input receivers and more consistency in the set-up and hold times.

Abstract: Integrated circuit regions are formed on an integrated circuit wafer. The integrated circuit wafer includes scribe regions located between the integrated circuit regions, the scribe regions include test pads that are electrically connected to the test circuits of integrated circuit regions via conductive lines. Test functions are provided to the test circuits in the integrated circuit regions via the test pads to determine the operability of the integrated circuit regions. The integrated circuit regions are separated from the plurality of scribe regions and the plurality of test pads located therein. Separating the integrated circuit regions from the scribe regions and the test pads, thereby may allow a reduction in the number of pads in the integrated circuits and a corresponding decrease in the size of respective integrated circuit packages.

Abstract: A semiconductor memory device having an improved column select control circuit. The semiconductor memory device includes a memory cell array consisting of a plurality of volatile memory cells and a column select line decoder for selecting a column line of the memory cell array. The semiconductor memory device includes at least two different refresh cycle modes designed within a single chip. A mode select circuit generates a mode select signal for selecting one of at least two refresh modes. A column select control circuit controls the enable time of the column select line decoder enable signal responsive to the mode select signal and to row address strobe signal for providing the column select line decoder enable signal to the column select line decoder.

Abstract: A semiconductor memory device is shown that includes a normal memory cell array including a plurality of memory cells specified by 2.sup.n word lines and a plurality of column bit lines where an externally input n-bit row address is decoded to activate one of the 2.sup.n word lines. The semiconductor memory device further includes a redundant row fuse decoder that includes a plurality of n-bit address fuse portions each of which can be selectively coded to respond to an n-bit defective row address value in the externally input n-bit row address which corresponds to a word line in the normal memory cell array that includes a defective memory cell. The semiconductor memory device further includes a redundant memory cell array including a plurality of rows of memory cells which can be activated by one of the n-bit address fuse portions in response to the defective row address coded into the n-bit address fuse portion.