Patents by Inventor Ho Tae Jin
Ho Tae Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9252123Abstract: A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.Type: GrantFiled: October 3, 2014Date of Patent: February 2, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won-Gil Han, Se-Yeoul Park, Ho-Tae Jin, Byong-Joo Kim, Yong-Je Lee, Han-Ki Park
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Publication number: 20150031149Abstract: A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.Type: ApplicationFiled: October 3, 2014Publication date: January 29, 2015Inventors: Won-Gil HAN, Se-Yeoul PARK, Ho-Tae JIN, Byong-Joo KIM, Yong-Je LEE, Han-Ki PARK
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Publication number: 20140191397Abstract: A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.Type: ApplicationFiled: March 12, 2014Publication date: July 10, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Gyu KANG, Ho-Tae JIN, Tae-ho MOON, Il-Soo CHOI, Jong-Eun LEE
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Publication number: 20140193984Abstract: An apparatus for reducing residual stress of a semiconductor includes a stage configured to support a semiconductor wafer having the residual stress generated by a semiconductor manufacturing process. The apparatus includes an intense pulsed light (IPL) irradiation unit configured to irradiate IPL to the semiconductor wafer to reduce the residual stress of the semiconductor wafer, the IPL radiation unit being separated from the stage. The apparatus further includes at least one alignment unit configured to adjust relative positions of the stage and the IPL irradiation unit.Type: ApplicationFiled: December 30, 2013Publication date: July 10, 2014Applicants: Industry-University Cooperation Foundation Hanyang University, SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Dong PARK, Hak Sung KIM, Jeong Sam LEE, Eun Beom JEON, Ho-Tae JIN
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Patent number: 8698311Abstract: A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.Type: GrantFiled: August 30, 2012Date of Patent: April 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Gyu Kang, Ho-Tae Jin, Tae-ho Moon, Il-soo Choi, Jong-Eun Lee
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Patent number: 8466074Abstract: A method for processing a substrate includes generating a first laser beam, splitting the first laser beam into a plurality of second laser beams, focusing the split second laser beams on a plane in the substrate parallel to a main surface of the substrate, and performing surface separation of the substrate along the plane.Type: GrantFiled: April 8, 2011Date of Patent: June 18, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-il Cho, Ho-tae Jin, Heui-seog Kim, Seon-ju Oh
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Publication number: 20130093080Abstract: A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.Type: ApplicationFiled: September 14, 2012Publication date: April 18, 2013Inventors: Won-Gil HAN, Se-Yeoul Park, Ho-Tae Jin, Byong-Joo Kim, Yong-Je Lee, Han-Ki Park
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Publication number: 20130069229Abstract: A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.Type: ApplicationFiled: August 30, 2012Publication date: March 21, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Gyu KANG, Ho-Tae JIN, Tae-ho MOON, Il-soo CHOI, Jong-Eun LEE
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Publication number: 20110256736Abstract: A method for processing a substrate includes generating a first laser beam, splitting the first laser beam into a plurality of second laser beams, focusing the split second laser beams on a plane in the substrate parallel to a main surface of the substrate, and performing surface separation of the substrate along the plane.Type: ApplicationFiled: April 8, 2011Publication date: October 20, 2011Inventors: Sung-il Cho, Ho-tae Jin, Heui-seog Kim, Seon-ju Oh
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Patent number: 7502231Abstract: Provided is a thin printed circuit board (PCB) for manufacturing a chip scale package (CSP). The thin printed circuit board includes a plurality of unit printed circuit boards, each of which is comprised of a circuit pattern, to which a semiconductor chip is adhered, and a substrate surrounding the circuit pattern. The unit printed boards are arranged in a row and includes a support molding, which is spaced a predetermined interval apart from the circuit pattern of each unit printed circuit board on the substrate of each unit printed circuit board and formed in a ring shape along the edge of the thin printed circuit board.Type: GrantFiled: December 5, 2007Date of Patent: March 10, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yi-Sung Hwang, Ho-Tae Jin, Hwan-Young Jang
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Publication number: 20090028671Abstract: An in-line system for manufacturing a semiconductor package according to principles of the present invention can prevent wafer warpage due to a back-lap process and die defects due to sticking of the die. In one embodiment, the in-line system adheres a semiconductor chip to a substrate by coating a liquid adhesive agent on a rear surface of the wafer. The processes of the in-line system are preferably performed in series. More particularly, the in-line system for manufacturing a semiconductor package can include a loading unit for loading a wafer into the system. A back-lap unit can include a grinder configured to back-grind a rear surface of the wafer received from the loading unit. A cleansing unit preferably comprises an air pressure plasma generating unit for cleansing the wafer using air pressure plasma. A coating unit can be configured to form an adhesive layer on a rear surface of the cleansed wafer by using a nozzle to coat a liquid adhesive agent onto the wafer.Type: ApplicationFiled: November 20, 2007Publication date: January 29, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho-Tae Jin, Young-Seok Jung, Bong-Su Cho
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Publication number: 20080142945Abstract: Provided are a semiconductor package in which wiring layers connected to a semiconductor chip electrically contact circuit patterns of a substrate and a method of manufacturing the same. The semiconductor package includes the substrate and the semiconductor chip. The substrate includes a first concave portion disposed on the upper surface thereof and a plurality of the circuit patterns disposed adjacent to the first concave portion. The semiconductor chip is mounted in the substrate to correspond to the concave portion. The semiconductor chip comprises a wafer, pads disposed on the wafer, and wiring layers disposed on the upper surface and on one side surface of the wafer, wherein first portions disposed on the upper surface of the wafer are connected to the pads and second portions disposed on the one side surface of the wafer contact the circuit patterns of the substrate.Type: ApplicationFiled: December 19, 2007Publication date: June 19, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Weon HA, Sang-Gug LEE, Ho-Tae Jin, Doo-Ho KANG
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Publication number: 20080083561Abstract: Provided is a thin printed circuit board (PCB) for manufacturing a chip scale package (CSP). The thin printed circuit board includes a plurality of unit printed circuit boards, each of which is comprised of a circuit pattern, to which a semiconductor chip is adhered, and a substrate surrounding the circuit pattern. The unit printed boards are arranged in a row and includes a support molding, which is spaced a predetermined interval apart from the circuit pattern of each unit printed circuit board on the substrate of each unit printed circuit board and formed in a ring shape along the edge of the thin printed circuit board.Type: ApplicationFiled: December 5, 2007Publication date: April 10, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yi-Sung Hwang, Ho-Tae JIN, Hwan-Young JANG
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Patent number: 7323642Abstract: Provided is a thin printed circuit board (PCB) for manufacturing a chip scale package (CSP). The thin printed circuit board includes a plurality of unit printed circuit boards, each of which is comprised of a circuit pattern, to which a semiconductor chip is adhered, and a substrate surrounding the circuit pattern. The unit printed boards are arranged in a row and includes a support molding, which is spaced a predetermined interval apart from the circuit pattern of each unit printed circuit board on the substrate of each unit printed circuit board and formed in a ring shape along the edge of the thin printed circuit board.Type: GrantFiled: July 16, 2004Date of Patent: January 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Yi-Sung Hwang, Ho-Tae Jin, Hwan-young Jang
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Publication number: 20050011668Abstract: Provided is a thin printed circuit board (PCB) for manufacturing a chip scale package (CSP). The thin printed circuit board includes a plurality of unit printed circuit boards, each of which is comprised of a circuit pattern, to which a semiconductor chip is adhered, and a substrate surrounding the circuit pattern. The unit printed boards are arranged in a row and includes a support molding, which is spaced a predetermined interval apart from the circuit pattern of each unit printed circuit board on the substrate of each unit printed circuit board and formed in a ring shape along the edge of the thin printed circuit board.Type: ApplicationFiled: July 16, 2004Publication date: January 20, 2005Applicant: Samsung Electronics Co., Ltd.Inventors: Yi-Sung Hwang, Ho-Tae Jin, Hwan-young Jang
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Publication number: 20040224439Abstract: A semiconductor package including a double-faced semiconductor chip having integrated circuitry on both sides thereof, and a method of fabricating the same is provided, wherein the semiconductor package includes the semiconductor chip; a lead-on-chip (LOC)-type substrate, having metal patterns on both sides, bonded with the first side of the semiconductor chip; first wires for connecting the first side of the semiconductor chip to the second side of the LOC-type substrate; second wires for connecting the second side of the semiconductor chip to the first side of the LOC-type substrate; a first sealing material for covering the semiconductor chip, the first wires, and the second side of the LOC-type substrate; a second sealing material for covering the semiconductor chip, the second wires, and the first side of the LOC-type substrate; and solder balls attached to the second side of the LOC-type substrate.Type: ApplicationFiled: June 3, 2004Publication date: November 11, 2004Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho-tae Jin, Heui-seog Kim
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Patent number: 6787393Abstract: A semiconductor package including a double-faced semiconductor chip having integrated circuitry on both sides thereof, and a method of fabricating the same is provided, wherein the semiconductor package includes the semiconductor chip; a lead-on-chip (LOC)-type substrate, having metal patterns on both sides, bonded with the first side of the semiconductor chip; first wires for connecting the first side of the semiconductor chip to the second side of the LOC-type substrate; second wires for connecting the second side of the semiconductor chip to the first side of the LOC-type substrate; a first sealing material for covering the semiconductor chip, the first wires, and the second side of the LOC-type substrate; a second sealing material for covering the semiconductor chip, the second wires, and the first side of the LOC-type substrate; and solder balls attached to the second side of the LOC-type substrate.Type: GrantFiled: February 24, 2003Date of Patent: September 7, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-tae Jin, Heui-seog Kim
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Publication number: 20030189250Abstract: A semiconductor package including a double-faced semiconductor chip having integrated circuitry on both sides thereof, and a method of fabricating the same is provided, wherein the semiconductor package includes the semiconductor chip; a lead-on-chip (LOC)-type substrate, having metal patterns on both sides, bonded with the first side of the semiconductor chip; first wires for connecting the first side of the semiconductor chip to the second side of the LOC-type substrate; second wires for connecting the second side of the semiconductor chip to the first side of the LOC-type substrate; a first sealing material for covering the semiconductor chip, the first wires, and the second side of the LOC-type substrate; a second sealing material for covering the semiconductor chip, the second wires, and the first side of the LOC-type substrate; and solder balls attached to the second side of the LOC-type substrate.Type: ApplicationFiled: February 24, 2003Publication date: October 9, 2003Inventors: Ho-Tae Jin, Heui-Seog Kim
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Patent number: 6392286Abstract: The present invention uses an ultraviolet ray to clean PCBs in packaging semiconductors, instead of using a plasma gas. Since the ultraviolet ray cleaning does not require a vacuum condition around an ultraviolet ray lamp, a guide belt for conveying the PCBs can be freely installed in such a manner that an ultraviolet ray cleaning tool and fabricating equipment are arranged in-line. This results in an in-line arrangement of an ultraviolet ray cleaning chamber and the fabricating equipment. Therefore, the PCBs can be introduced into fabricating processes immediately after cleaning and a long standby time problem of the PCB outside of the fabricating equipment is solved.Type: GrantFiled: August 2, 2000Date of Patent: May 21, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Tae Jin, Heui-Seong Kim, Sang-Young Kim
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Patent number: 6386432Abstract: An embodiment of the present invention provides a pickup tool in accordance with the present invention includes multiple contact parts, which contact a passivation layer of a semiconductor chip so that the contact parts are far from chip pads and fuses when holding the semiconductor chip. Furthermore, a die bonding apparatus has one or two pickup tools, an aligning stage, and a bond stage or a bond head.Type: GrantFiled: November 10, 2000Date of Patent: May 14, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Ho Tae Jin, Hee Kook Choi