Patents by Inventor Ho Wang Wong

Ho Wang Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240150937
    Abstract: Provided herein are protective masks made with polymer-based materials and methods of forming the materials. Methods of forming the interlaced polymer-based materials comprise applying adhesive to a substrate, electrospinning a first polymer solution onto the substrate from a first group of spinning electrodes, electrospinning a second polymer solution onto the substrate from a second group of spinning electrodes, and applying hot air to dry the polymer-based materials electrospun from the first polymer solution and the second polymer solution to form the interlaced polymer-based materials.
    Type: Application
    Filed: May 18, 2022
    Publication date: May 9, 2024
    Inventors: Siu Wah WONG, Ho Wang TONG, Chi Hang YU, Yu Hang LEUNG, Wing Man CHAN
  • Publication number: 20110042793
    Abstract: A lead frame assembly includes a first lead frame panel having a die receiving area for receiving a semiconductor die, the die having an upper surface having one or more die bond pads located thereon. A second lead frame panel includes integral leads, each integral lead including a terminal, a connecting element extending from the terminal, and a shaped contact located at an end of the connecting element. The second lead frame panel is adapted to be stacked on the first lead frame panel to position each terminal laterally of a respective die receiving area. The positioning of the terminals locates each shaped contact for contact with a respective die bond pad to establish an electrical connection between the die bond pad and the respective terminal when the semiconductor die is mounted on the respective die receiving area.
    Type: Application
    Filed: August 21, 2009
    Publication date: February 24, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Kai Man WONG, Kam Fai LEE, Ho Wang WONG
  • Patent number: 7301225
    Abstract: A lead frame (10) for a semiconductor device includes a first row of terminals (12) surrounding a die receiving area (14) and a second row of terminals (16) spaced from and surrounding the first row of terminals (12). The first and second rows of terminals (12, 16) have a first height (H1). The terminals (12) of the first row include a step (26) that has a greater height (H2). Bond wires (36) connecting die pads (34) to the first row terminals (12) extend over the second height H2 part of the terminal (12) and are attached to the first height H1 part of the terminal (12). The step (26) insures that the bond wires (36) attached to the stepped terminals (12) have a high wire kink profile so that they are less susceptible to damage in later process steps.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: November 27, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Fei Ying Wong, Wai Keung Ho, Ho Wang Wong
  • Patent number: 7205178
    Abstract: A method of packaging an integrated circuit die (12) includes the steps of providing a foil sheet (30) and forming a layer of solder (32) on a first side of the foil sheet. A first side of the integrated circuit die is attached to the solder on the foil sheet. The first side of the die has a layer of metal (34) on it and a second, opposing side of the die includes bonding pads (14). The bonding pads are electrically connected to the solder on the foil sheet with wires (16). The die, the electrical connections, and the first side of the foil sheet are encapsulated with a mold compound (20). The foil sheet is separated from the die and the wires, which forms a packaged integrated circuit (10).
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: April 17, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hei Ming Shiu, Kam Fai Lee, Ho Wang Wong