Patents by Inventor Ho Wei De

Ho Wei De has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160274455
    Abstract: A method of optimizing a semiconductor mask layout is provided. The method includes accessing a digital file comprising the semiconductor mask layout, accessing processing condition parameters describing process conditions, receiving a request from a user of a mask layout system to initiate a semiconductor mask layout optimization process, applying a set of rules to insert an array of assist features into the semiconductor mask layout, and updating the digital file. The semiconductor mask layout includes a plurality of parallel mask features, wherein pairs of the parallel mask features share an end-to-end region between the parallel mask features of each pair, with an imaginary axis bisecting the end-to-end regions. Each assist feature is located proximate to at least one end-to-end region, and the imaginary axis intersects each assist feature. Related photomasks, design layout systems, and computer-readable media are also provided.
    Type: Application
    Filed: March 16, 2015
    Publication date: September 22, 2016
    Inventors: Ho Wei-De, Chi-Yuan Sun, Ya Hui Chang, Hung-Chang Hsieh
  • Patent number: 9236267
    Abstract: A method for patterning a plurality of features in a non-rectangular pattern, such as on an integrated circuit device, includes providing a substrate including a surface with a plurality of elongated protrusions, the elongated protrusions extending in a first direction. A first layer is formed above the surface and above the plurality of elongated protrusions, and patterned with an end cutting mask. The end cutting mask includes two nearly-adjacent patterns with a sub-resolution feature positioned and configured such that when the resulting pattern on the first layer includes the two nearly adjacent patterns and a connection there between. The method further includes cutting ends of the elongated protrusions using the pattern on the first layer.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: January 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ho Wei De, Kuei-Liang Lu, Ming-Feng Shieh, Ching-Yu Chang
  • Patent number: 8741776
    Abstract: A method for patterning a plurality of features in a non-rectangular pattern on an integrated circuit device includes providing a substrate including a surface with a first layer and a second layer. Forming a plurality of elongated protrusions in a third layer above the first and second layers. Forming a first patterned layer over the plurality of elongated protrusions. The plurality of elongated protrusions are etched to form a first pattern of the elongated protrusions, the first pattern including at least one inside corner. Forming a second patterned layer over the first pattern of elongated protrusions and forming a third patterned layer over the first pattern of elongated protrusions. The plurality of elongated protrusions are etched using the second and third patterned layers to form a second pattern of the elongated protrusions, the second pattern including at least one inside corner.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ho Wei De, Ming-Feng Shieh, Ching-Yu Chang
  • Publication number: 20130210232
    Abstract: A method for patterning a plurality of features in a non-rectangular pattern, such as on an integrated circuit device, includes providing a substrate including a surface with a plurality of elongated protrusions, the elongated protrusions extending in a first direction. A first layer is formed above the surface and above the plurality of elongated protrusions, and patterned with an end cutting mask. The end cutting mask includes two nearly-adjacent patterns with a sub-resolution feature positioned and configured such that when the resulting pattern on the first layer includes the two nearly adjacent patterns and a connection there between. The method further includes cutting ends of the elongated protrusions using the pattern on the first layer.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 15, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ho Wei De, Kuei-Liang Lu, Ming-Feng Shieh, Ching-Yu Chang
  • Publication number: 20130203257
    Abstract: A method for patterning a plurality of features in a non-rectangular pattern on an integrated circuit device includes providing a substrate including a surface with a first layer and a second layer, forming a plurality of elongated protrusions in a third layer above the first and second layers, and forming a first patterned layer over the plurality of elongated protrusions. The plurality of elongated protrusions are etched to form a first pattern of the elongated protrusions, the first pattern including at least one inside corner. The method also includes forming a second patterned layer over the first pattern of elongated protrusions and forming a third patterned layer over the first pattern of elongated protrusions. The plurality of elongated protrusions are etched using the second and third patterned layers to form a second pattern of the elongated protrusions, the second pattern including at least one inside corner.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 8, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ho Wei De, Ming-Feng Shieh, Ching-Yu Chang