Patents by Inventor Howon Kim

Howon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11392706
    Abstract: Disclosed is a hardware module with a 32-bit unit operation for processor supporting ARIA encryption and decryption, including: an instruction pipeline that executes an instruction fetch, instruction decoding, and an instruction execution; and an ARIA operation module that has a 32-bit unit operation system provided in the instruction execution pipeline to support ARIA encryption and decryption. Two types of instructions, ARIA substitution layer and diffusion layer instructions are provided as a 32-bit unit operation instruction in order to provide an ARIA encryption/decryption function through the ARIA operation module, the substitution layer instruction includes two instructions for an even round and an odd round of the ARIA encryption/decryption, and the diffusion layer includes four types of diffusion layer instructions for the even sub-round and four types of diffusion layer instructions for the odd sub-round.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: July 19, 2022
    Assignee: PUSAN NATIONAL UNIVERSITY INDUSTRY—UNIVERSITY COOPERATION FOUNDATION
    Inventors: Howon Kim, Haeyoung Kim, Jinjae Lee
  • Patent number: 11368303
    Abstract: Disclosed are a system and method for calculating elliptic curve cryptography scalar multiplication using an FPGA (Field Programmable Gate Array), the system and method scheduling calculation, which is used in a Montgomery ladder Algorithm, and enabling efficient calculation through an improved modular arithmetic calculation method. The system for calculating elliptic curve cryptography (ECC) scalar multiplication using an FPGA includes: a scheduler implementing Montgomery ladder step calculation in a pipeline structure; a pipeline modular adder/subtractor implementing n-bit modular addition in a d-stage pipeline structure; and a modular multiplier implementing n-bit modular multiplication in a 10-stage pipeline structure up to maximum 256 bits.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: June 21, 2022
    Assignee: Pusan National University Industry-University Cooperation Foundation
    Inventors: Howon Kim, Asep Muhamad Awaludin, Youngyeo Yun
  • Publication number: 20220164454
    Abstract: Disclosed is a hardware module with a 32-bit unit operation for processor supporting ARIA encryption and decryption, including: an instruction pipeline that executes an instruction fetch, instruction decoding, and an instruction execution; and an ARIA operation module that has a 32-bit unit operation system provided in the instruction execution pipeline to support ARIA encryption and decryption. Two types of instructions, ARIA substitution layer and diffusion layer instructions are provided as a 32-bit unit operation instruction in order to provide an ARIA encryption/decryption function through the ARIA operation module, the substitution layer instruction includes two instructions for an even round and an odd round of the ARIA encryption/decryption, and the diffusion layer includes four types of diffusion layer instructions for the even sub-round and four types of diffusion layer instructions for the odd sub-round.
    Type: Application
    Filed: October 26, 2021
    Publication date: May 26, 2022
    Applicant: Pusan National University Industry-University Cooperation Foundation
    Inventors: Howon KIM, Haeyoung KIM, Jinjae LEE
  • Publication number: 20220166619
    Abstract: Disclosed are a system and method for calculating elliptic curve cryptography scalar multiplication using an FPGA (Field Programmable Gate Array), the system and method scheduling calculation, which is used in a Montgomery ladder Algorithm, and enabling efficient calculation through an improved modular arithmetic calculation method. The system for calculating elliptic curve cryptography (ECC) scalar multiplication using an FPGA includes: a scheduler implementing Montgomery ladder step calculation in a pipeline structure; a pipeline modular adder/subtractor implementing n-bit modular addition in a d-stage pipeline structure; and a modular multiplier implementing n-bit modular multiplication in a 10-stage pipeline structure up to maximum 256 bits.
    Type: Application
    Filed: October 26, 2021
    Publication date: May 26, 2022
    Applicant: Pusan National University Industry-University Cooperation Foundation
    Inventors: Howon KIM, ASEP MUHAMAD AWALUDIN, Youngyeo YUN
  • Patent number: 10572797
    Abstract: Provided are an apparatus and method for classifying home appliances based on power consumption using deep learning, which can efficiently classify home appliances in use by applying deep learning and analyzing power data collected from a house. The apparatus includes a home appliance classification model creation module configured to encode power consumption data collected from a house to learn a home appliance classification model and create an RNN-based home appliance classification model and a home appliance classification module configured to collect and encode data on power consumption currently in use and classify home appliances using the home appliance classification model created by the home appliance classification model creation module.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: February 25, 2020
    Assignee: Pusan National University Industry—University Cooperation Foundation
    Inventors: Howon Kim, Jihyun Kim
  • Publication number: 20170116511
    Abstract: Provided are an apparatus and method for classifying home appliances based on power consumption using deep learning, which can efficiently classify home appliances in use by applying deep learning and analyzing power data collected from a house. The apparatus includes a home appliance classification model creation module configured to encode power consumption data collected from a house to learn a home appliance classification model and create an RNN-based home appliance classification model and a home appliance classification module configured to collect and encode data on power consumption currently in use and classify home appliances using the home appliance classification model created by the home appliance classification model creation module.
    Type: Application
    Filed: October 27, 2016
    Publication date: April 27, 2017
    Applicant: Pusan National University Industry-University Cooperation Foundation
    Inventors: Howon KIM, Jihyun KIM
  • Publication number: 20100332576
    Abstract: Disclosed is an apparatus and a method of calculating the square root of an element a, which is not zero, belonging to a finite extension field FpAk (where p is a prime number satisfying p?3(mod 4) and k is an odd number). The method includes: calculating a common exponentiation formula that is common to an exponentiation formula for calculating a quadratic residue, which is used to determine whether the square root of the element a is present, and an exponentiation formula for calculating the square root of the element a when it is determined that the square root of the element a is present; determining the result obtained by multiplying the square of the common exponentiation formula by the element a as the quadratic residue; and determining the result obtained by multiplying the common exponentiation formula by the element a as the square root of the element a.
    Type: Application
    Filed: August 28, 2008
    Publication date: December 30, 2010
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Dongguk Han, Howon Kim, Kyoil Chung
  • Patent number: 7126630
    Abstract: A method and apparatus for omni-directional image and 3-dimensional data acquisition with data annotation and dynamic rage extension method is capable of omni-directionally photographing, acquiring 3-dimensional images photographed by cameras having each different exposure amount in connection with the direction of height of an object, extending dynamic range, and generating an geographical information by entering an annotation such as photographing location and time into the photographed images, which can be connected with other geographical information system database. The apparatus includes one or more multi camera module(s) which are stacked and formed multi layers in the direction of height for acquiring 3-dimensional images and extending dynamic range of the 3-dimensional images, wherein each multi camera module includes a plurality of cameras symmetrically arranged with a specific point in a plane.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: October 24, 2006
    Inventors: Kujin Lee, In So Kweon, Howon Kim, Junsik Kim