Abstract: A semiconductor memory device of a high degree of freedom in column and a graphics display system using the semiconductor memory device as a mapping memory are provided. The semiconductor memory device according to the present invention is comprised of a plurality of memory arrays and each memory array is comprised of a plurality of memory cell groups. A plurality memory cell groups in each memory array are independently selected according to the information of a separate column address. Column decoders select the column of a corresponding memory array in response to common column addresses and first or second separate column addresses. The first or the second separate column addresses select one memory cell group among memory cell groups in each memory array. The common column addresses select predetermined numbers of columns in each memory cell group.

Abstract: The present invention discloses a semiconductor memory device. The device comprises a predetermined number of groups of a plurality of memory cell array blocks and a plurality of column decoders. The groups of the plurality of memory cell array blocks are connected to a predetermined number of column select signal lines among a plurality of column select signal lines, respectively. Each of the memory cell array blocks includes a plurality of memory cells connected between a plurality of word lines arranged in the same direction with the column select signal lines and a plurality of bit line pairs. The plurality of column decoders select corresponding column select signal lines between the plurality of memory cell array blocks in response to corresponding block select signal for selecting each of the plurality of memory cell array blocks and corresponding column address.

Abstract: The present invention discloses a semiconductor memory device. The device comprises a predetermined number of groups of a plurality of memory cell array blocks and a plurality of column decoders. The groups of the plurality of memory cell array blocks are connected to a predetermined number of column select signal lines among a plurality of column select signal lines, respectively. Each of the memory cell array blocks includes a plurality of memory cells connected between a plurality of word lines arranged in the same direction with the column select signal lines and a plurality of bit line pairs. The plurality of column decoders select corresponding column select signal lines between the plurality of memory cell array blocks in response to corresponding block select signal for selecting each of the plurality of memory cell array blocks and corresponding column address.

Abstract: The present invention discloses a semiconductor memory device. The device comprises a predetermined number of groups of a plurality of memory cell array blocks and a plurality of column decoders. The groups of the plurality of memory cell array blocks are connected to a predetermined number of column select signal lines among a plurality of column select signal lines, respectively. Each of the memory cell array blocks includes a plurality of memory cells connected between a plurality of word lines arranged in the same direction with the column select signal lines and a plurality of bit line pairs. The plurality of column decoders select corresponding column select signal lines between the plurality of memory cell array blocks in response to corresponding block select signal for selecting each of the plurality of memory cell array blocks and corresponding column address.

Abstract: A synchronous memory device capable of performing write operation with a programmable write cycle, and a data write method using the synchronous memory device. The synchronous memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, a precharge circuit for precharging a data input/output line which transmits data to be written to the memory cells, with a predetermined voltage level, and a column selection circuit for writing the data transmitted to the data input/output line to a selected memory cell, in response to activation of a column selection signal. The activation cycle of the column selection signal is determined according to the write cycle modes programmed in a mode register set. The write cycle modes can be programmed in the mode register set with system clock frequency information, so that the number of data write operations per clock cycle can be varied.

Abstract: The present invention relates to a control circuit and method for controlling a data line switching circuit in a semiconductor memory device having a memory cell array, a row decoder for designating a row of a memory cell, a column decoder for designating a column thereof, a bit line sense amplifier which senses a signal of a bit line and amplifies it, and a column selection gate circuit which comprises a plurality of MOS transistors and selectively applies output signals of the bit line sense amplifier to input/output lines via a MOS transistor gated by an output signal of the column decoder among the plurality of MOS transistors.

Abstract: An integrated circuit data output buffer which may be used in an integrated circuit memory device, includes a data output circuit which is responsive to a data input signal to generate a data output signal, using a boosting data signal. A pulse generator generates a pulse in response to a control signal. A power supply sensing circuit is connected to the pulse generator, and generates a power supply voltage sensing signal in response to the pulse. A clamp circuit is connected to the power supply voltage sensing circuit and to the data output circuit, to clamp the boosting power signal after a predetermined time in response to the power supply voltage sensing signal. Accordingly, output data is buffered by generating a pulse in response to a control signal and generating a power supply voltage sensing signal in response to the pulse.