Patents by Inventor Ho-Yeong Choe

Ho-Yeong Choe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8048802
    Abstract: A method for forming an interlayer insulating film includes providing a semiconductor substrate having a first substrate region with a plurality of metal wiring and a second substrate region having no metal wiring, and then forming an insulating film dummy pattern in the second substrate region, wherein the insulating film dummy pattern has the same thickness as the metal wiring, and then forming an interlayer insulating film over the semiconductor substrate including the insulating film dummy pattern.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: November 1, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Ho-Yeong Choe
  • Patent number: 8008148
    Abstract: A method for manufacturing a semiconductor device includes sequentially forming an insulating layer and a metal layer over a semiconductor substrate, forming a photoresist pattern over the metal layer and etching the metal layer using the photoresist pattern as an etching mask to form a metal line pattern, subjecting the photoresist pattern to a reflow process to form a photoresist pattern over the metal layer and etching the metal layer using the photoresist pattern as an etching mask to form a metal line pattern, subjecting the photoresist pattern to a reflow process to form a reflowed photoresist pattern surrounding the metal line pattern, forming a metal-insulator-metal (MIM) layer over the semiconductor substrate provided with the reflowed photoresist pattern, and removing the MIM layer arranged over the photoresist pattern and the photoresist pattern.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: August 30, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Ho-Yeong Choe
  • Publication number: 20090283857
    Abstract: A method for manufacturing a semiconductor device includes sequentially forming an insulating layer and a metal layer over a semiconductor substrate, forming a photoresist pattern over the metal layer and etching the metal layer using the photoresist pattern as an etching mask to form a metal line pattern, subjecting the photoresist pattern to a reflow process to form a photoresist pattern over the metal layer and etching the metal layer using the photoresist pattern as an etching mask to form a metal line pattern, subjecting the photoresist pattern to a reflow process to form a reflowed photoresist pattern surrounding the metal line pattern, forming a metal-insulator-metal (MIM) layer over the semiconductor substrate provided with the reflowed photoresist pattern, and removing the MIM layer arranged over the photoresist pattern and the photoresist pattern.
    Type: Application
    Filed: May 7, 2009
    Publication date: November 19, 2009
    Inventor: Ho-Yeong Choe
  • Publication number: 20090057927
    Abstract: A method for forming an interlayer insulating film includes providing a semiconductor substrate having a first substrate region with a plurality of metal wiring and a second substrate region having no metal wiring, and then forming an insulating film dummy pattern in the second substrate region, wherein the insulating film dummy pattern has the same thickness as the metal wiring, and then forming an interlayer insulating film over the semiconductor substrate including the insulating film dummy pattern.
    Type: Application
    Filed: August 25, 2008
    Publication date: March 5, 2009
    Inventor: Ho-Yeong Choe
  • Publication number: 20080157277
    Abstract: Embodiments relate to a metal-insulator-metal (MIM) capacitor that may include a lower insulation layer where a capacitor lower metal layer is already formed, an intermediate structure, a first conductive structure, and a second conductive structure. The intermediate structure may include a first capacitor insulation pattern, a capacitor middle metal layer, a second capacitor insulation pattern, a capacitor upper metal layer, and an insulation pattern formed in sequence over the lower insulation layer. The first conductive structure may include a copper-based material and may be coupled between the capacitor upper metal layer and the capacitor lower metal layer. The second conductive structure may include a copper-based material and is coupled to the capacitor middle metal layer.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 3, 2008
    Inventors: Jeong-Ho Park, Ho-Yeong Choe