Abstract: Disclosed are a semiconductor memory device and an operation method thereof. The semiconductor memory device includes a main buffer suitable for storing input data during a first operation period of a write operation, a repair operation unit suitable for selectively latching the input data based on whether the input data is used for repair during the first operation period of the write operation; a repair buffer suitable for storing the latched input data during a second operation period subsequent to the first operation period, and a column operation unit suitable for controlling an operation to write the input data stored in the main buffer or the repair buffer in a main memory cell or a repair memory cell during the second operation period of the write operation.

Abstract: Disclosed are a semiconductor memory device and an operation method thereof. The semiconductor memory device includes a main buffer suitable for storing input data during a first operation period of a write operation, a repair operation unit suitable for selectively latching the input data based on whether the input data is used for repair during the first operation period of the write operation; a repair buffer suitable for storing the latched input data during a second operation period subsequent to the first operation period, and a column operation unit suitable for controlling an operation to write the input data stored in the main buffer or the repair buffer in a main memory cell or a repair memory cell during the second operation period of the write operation.

Abstract: A semiconductor memory apparatus includes: a memory block including first and second planes; and a reset signal generator configured to generate a first reset signal by logically combining a first plane selection signal and a control pulse signal which pulses after a first programming setup pulse signal pulses during a first programming command cycle, and generate a second reset signal by logically combining a second plane selection signal and the control pulse signal which again pulses after a second programming setup pulse signal pulses during a second programming command cycle after the first programming command cycle. A plurality of first page buffers allocated to the first plane are reset in response to the first reset signal, and a plurality of second page buffers allocated to the second plane are reset in response to the second reset signal.

Abstract: A semiconductor memory device includes a count clock generation unit for generating a count clock in response to a clock signal and a dummy count clock, a column address generation unit for generating a column address in response to the count clock, and a Y decoder for sending data, stored in a page buffer unit, to a data line in response to the column address.

Abstract: A semiconductor memory device includes a count clock generation unit for generating a count clock in response to a clock signal and a dummy count clock, a column address generation unit for generating a column address in response to the count clock, and a Y decoder for sending data, stored in a page buffer unit, to a data line in response to the column address.

Abstract: A nonvolatile memory device comprises a page buffer unit comprising page buffers, each coupling first and second input and output (IO) lines and a latch circuit for outputting data together or coupling a sense node and the first or second I/O line together, in response to an operation mode; a Y decoder unit comprising decoders, each selecting one or more of the page buffers in response to address signals and outputting a first or second control signal to the selected page buffers in response to the operation mode; a mode selection unit outputting first and second operation selection signals for selecting the operation mode; and an I/O control unit comprising I/O control circuits, each detecting data, inputted and output through the first and second I/O lines, and outputting the detected data or coupling one of the first and second I/O lines to a data line.

Abstract: A semiconductor memory apparatus includes: a memory block including first and second planes; and a reset signal generator configured to generate a first reset signal by logically combining a first plane selection signal and a control pulse signal which pulses after a first programming setup pulse signal pulses during a first programming command cycle, and generate a second reset signal by logically combining a second plane selection signal and the control pulse signal which again pulses after a second programming setup pulse signal pulses during a second programming command cycle after the first programming command cycle. A plurality of first page buffers allocated to the first plane are reset in response to the first reset signal, and a plurality of second page buffers allocated to the second plane are reset in response to the second reset signal.

Abstract: An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.

Abstract: A semiconductor memory device is capable of controlling a tAC with a timing margin in an output data process. The semiconductor memory device includes a delay locked loop circuit, a tAC control unit, a reference signal generating unit, and a data output block. The delay locked loop circuit produces delay locked clock signals through a delay locking operation. The tAC control unit adjusts a delay value of the delay locked clock signals in order to control a tAC timing, thereby generating output reference signals. The reference signal generating unit produces a latch reference signal in response to the delay locked clock signals. The data output block latches data in response to the latch reference signal and for outputting the latched data in response to the output reference signals.

Abstract: Disclosed is a nonvolatile memory device including a memory cell array including main and redundant memory cells, content addressable memory cells configured to store a defective column address corresponding to a defective memory cell among the main cells, and a repair controller configured to compare the defective column address with an input address to generate a matching control signal and generate a redundancy check-enable signal when the defective column address is inputted as the input address and configured to generate a repair control signal in response to the matching control signal and the redundancy check-enable signal.

Abstract: A semiconductor memory input/output device includes selection pads used to input and output signals for multiple operation modes and having multiple functions, a control signal generator for outputting setting signals and a mask control signal, a lower input/output unit including a lower output buffer for outputting a read data strobe signal to a selection pad and a lower input buffer for receiving a lower data mask signal from the selection pad, and selecting one operation of the lower output buffer and the lower input buffer, and an upper input/output unit including an upper output buffer for outputting an inverted read data strobe signal to the second selection pad and an upper input buffer for receiving an upper data mask signal from the second selection pad, and selecting one operation of the upper output buffer and the upper input buffer.

Abstract: A semiconductor memory apparatus includes a sense amplifier that receives a driving voltage through a sense amplifier power supply input terminal and detects and amplifies a difference between signals that are supplied to two input lines, a sense amplifier voltage supply unit that supplies a driving voltage and an overdriving voltage higher than the driving voltage to the sense amplifier through the sense amplifier power supply input terminal using a power supply voltage, and a driving voltage control unit that maintains a driving voltage level of the sense amplifier power supply input terminal in response to the level of the power supply voltage, after a voltage of the sense amplifier power supply input terminal is elevated to a power supply level responding to the overdriving voltage in order to perform the overdriving operation.

Abstract: A semiconductor memory device includes a preliminary signal generator configured to output a preliminary pipe-in signal enabled when a read command is applied. A delay unit is configured to delay the preliminary pipe-in signal and output the delayed preliminary pipe-in signal to match the timing of output data. A pipe-in signal generator generates a pipe-in signals that are enabled between a predetermined enable point and a next enable point of the delayed preliminary pipe-in signal output.

Abstract: A nonvolatile memory device comprises a page buffer unit comprising page buffers, each coupling first and second input and output (IO) lines and a latch circuit for outputting data together or coupling a sense node and the first or second I/O line together, in response to an operation mode; a Y decoder unit comprising decoders, each selecting one or more of the page buffers in response to address signals and outputting a first or second control signal to the selected page buffers in response to the operation mode; a mode selection unit outputting first and second operation selection signals for selecting the operation mode; and an I/O control unit comprising I/O control circuits, each detecting data, inputted and output through the first and second I/O lines, and outputting the detected data or coupling one of the first and second I/O lines to a data line.

Abstract: A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches for latching data. An input controller controls input timing of data transmitted from data line to the pipe latch unit. An output controller controls output timing of data latched in the pipe latch unit. An initialization controller controls the input controller and the output controller to thereby initialize the pipe latch unit in response to a read/write flag signal which is activated during a write operation.

Abstract: An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.

Abstract: An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.

Abstract: A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating an input control signal group; and a pipe latch unit for latching data on a data line when a corresponding input control signal is activated, and outputting latched data when a corresponding output control signal is activated, wherein the output controller includes a plurality of shifters, each for delaying an input data signal by half clock and one clock to output a first and second output signals in synchronization with the DLL clock signal and the driving signal; and a plurality of output control signal drivers for outputting the first and second output control signal groups based on the first and second output signals.

Abstract: Semiconductor memory device and method for operating the same comprise an auxiliary driver configured to output an internal strobe signals generated corresponding to a read command as a plurality of auxiliary strobe signal in response to a control signal, wherein the auxiliary driver bypass a first output auxiliary strobe signal, and delay to output the rest of the auxiliary strobe signal among the outputted auxiliary strobe signal and a strobe signal generator for driving the auxiliary strobe signal to output the delayed auxiliary strobe signal as a data strobe signals.

Abstract: A first input buffer receives sequentially inputted first data. A first data selector selectively transfers the first data from the first input buffer in accordance with a data input mode. A first data alignment circuit aligns and outputs the data from the first data selector. A second input buffer receives sequentially inputted second data in accordance with the data input mode. A second data selector selectively transfers the data of the first input buffer or of the second input buffer, in accordance with the data input mode. A first data alignment circuit aligns and outputs the data from the second data selector.