Abstract: A row hammer control method and a memory device are provided. The memory device monitors the row hammer address(es) having the number of accesses equal to or more than a predetermined number of times or having a higher number of accesses as compared with other access addresses during the first row hammer monitoring time frame and malicious row hammer address(es) accessed at random sampling time points during the second row hammer monitoring time frame and being the same as the row hammer address(es), notifies a memory controller of the malicious row hammer address(es) when the number of malicious row hammer addresses exceeds a threshold value, and causes a target refresh a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address(es) to be performed.

Abstract: The present invention relates to a composition for improving cow reproductive ability, capable of not only improving productivity by improving the reproductive ability of cows, but also preventing various problems that may occur by indiscriminate use of hormonal preparations, and alleviating the economic burden of breeders, such as feed costs.

Abstract: A method of operating an electronic device which includes a first host device, a second host device, a control logic circuit, and a memory cell array. The method may include distributing target data of the memory cell array into the first and second host devices, where the target data include a first data piece and a second data piece, generating a first request for the first data piece, generating a second request for the second data piece, receiving the first request and the second request during a reference time period, generating encoded data by performing a first exclusive OR (XOR) operation on the first data piece and the second data piece of the target data in the memory cell array, based on the first and second requests, and transmitting the encoded data to the first and second host devices.

Abstract: A method of operating an electronic device which includes a first host device, a second host device, a control logic circuit, and a memory cell array. The method may include distributing target data of the memory cell array into the first and second host devices, where the target data include a first data piece and a second data piece, generating a first request for the first data piece, generating a second request for the second data piece, receiving the first request and the second request during a reference time period, generating encoded data by performing a first exclusive OR (XOR) operation on the first data piece and the second data piece of the target data in the memory cell array, based on the first and second requests, and transmitting the encoded data to the first and second host devices.

Abstract: A row hammer control method and a memory device are provided. The memory device monitors the row hammer address(es) having the number of accesses equal to or more than a predetermined number of times or having a higher number of accesses as compared with other access addresses during the first row hammer monitoring time frame and malicious row hammer address(es) accessed at random sampling time points during the second row hammer monitoring time frame and being the same as the row hammer address(es), notifies a memory controller of the malicious row hammer address(es) when the number of malicious row hammer addresses exceeds a threshold value, and causes a target refresh a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address(es) to be performed.

Abstract: A method of operating a memory device which is configured to communicate with a host device, and which includes a memory cell array and a processing-in-memory (PIM) chip, including loading activation data and weight data from the memory cell array, by the PIM chip; generating pruned activation data by performing a first pruning operation on the activation data, by the PIM chip; providing the pruned activation data to the host device, by the PIM chip; generating pruned weight data by performing a second pruning operation on the weight data, by the PIM chip; providing the pruned weight data to the host device, by the PIM chip; and storing output data corresponding to a neural network operation performed based on the pruned activation data and the pruned weight data, by the memory cell array.

Abstract: A row hammer control method and a memory device are provided. The memory device monitors the row hammer address(es) having the number of accesses equal to or more than a predetermined number of times or having a higher number of accesses as compared with other access addresses during the first row hammer monitoring time frame and malicious row hammer address(es) accessed at random sampling time points during the second row hammer monitoring time frame and being the same as the row hammer address(es), notifies a memory controller of the malicious row hammer address(es) when the number of malicious row hammer addresses exceeds a threshold value, and causes a target refresh a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address(es) to be performed.

Abstract: A memory controller includes a fault predictor which predicts a fault which causes an error occurring in a memory device, an error correction code (ECC) manager which classifies a type of the fault based on the predicted fault, and a plurality of ECC engines which perform ECC in parallel depending on the classified type of the faults. The fault predictor includes a memory error profiler which receives raw data related to the error and processes the raw data into an error profile that is data available for machine learning, and a memory fault prediction network which receives the error profile as an input, performs the machine learning using the error profile, and predicts the fault which causes the error.

Abstract: Disclosed is a semiconductor memory device comprising a memory core including a plurality of random-access memory cells, an error correction code (ECC) circuit configured to generate parity of data written to the memory core, and a message authentication code (MAC) control circuit configured to generate a security key based on a physical unclonable function (PUF) source signal in response to a message authentication code generation command or detection of a hacking or security attack, and configured to control the ECC circuit to generate a MAC on target data using the security key, wherein the ECC circuit operates in one of an ECC mode for generating an ECC parity and a MAC mode for generating the MAC under the control of the MAC control circuit.

Abstract: A memory device includes memory cells connected to a first word-line, wherein the memory cells include a data region in which data is stored and a counting value backup region in which the number of times the first word-line is activated is backed up, a counting table for storing a first row address corresponding to the first word-line and a first counting value as a counting result of the number of times the first word-line is activated, and a comparator configured to compare the first counting value with a first backed-up counting value stored in the counting value backup region; and when the first counting value is greater than the first backed-up counting value, back up the first counting value in the counting value backup region, or when the first backed-up counting value is greater than the first counting value, overwrite the first backed-up counting value into the counting table.

Abstract: A memory device includes; a memory module including a memory array, and a memory controller that retrieves read data from memory cells of the memory array. The memory controller includes a fault detector that detects faulty addresses associated with faulty memory cells among the memory cells providing data errors.

Abstract: A row hammer control method and a memory device are provided. The memory device monitors the row hammer address(es) having the number of accesses equal to or more than a predetermined number of times or having a higher number of accesses as compared with other access addresses during the first row hammer monitoring time frame and malicious row hammer address(es) accessed at random sampling time points during the second row hammer monitoring time frame and being the same as the row hammer address(es), notifies a memory controller of the malicious row hammer address(es) when the number of malicious row hammer addresses exceeds a threshold value, and causes a target refresh a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address(es) to be performed.

Abstract: A memory controller includes a fault predictor which predicts a fault which causes an error occurring in a memory device, an error correction code (ECC) manager which classifies a type of the fault based on the predicted fault, and a plurality of ECC engines which perform ECC in parallel depending on the classified type of the faults. The fault predictor includes a memory error profiler which receives raw data related to the error and processes the raw data into an error profile that is data available for machine learning, and a memory fault prediction network which receives the error profile as an input, performs the machine learning using the error profile, and predicts the fault which causes the error.

Abstract: A memory device includes; a memory module including a memory array, and a memory controller that retrieves read data from memory cells of the memory array. The memory controller includes a fault detector that detects faulty addresses associated with faulty memory cells among the memory cells providing data errors.

Abstract: A memory device includes memory cells connected to a first word-line, wherein the memory cells include a data region in which data is stored and a counting value backup region in which the number of times the first word-line is activated is backed up, a counting table for storing a first row address corresponding to the first word-line and a first counting value as a counting result of the number of times the first word-line is activated, and a comparator configured to compare the first counting value with a first backed-up counting value stored in the counting value backup region; and when the first counting value is greater than the first backed-up counting value, back up the first counting value in the counting value backup region, or when the first backed-up counting value is greater than the first counting value, overwrite the first backed-up counting value into the counting table.

Abstract: The present invention may provide a motor comprising an inverter housing in which a substrate is disposed, a connector which is mounted on the inverter housing and electrically connects the substrate and a cable and wherein the connector includes a body and a first terminal coupled to the body, one side of the first terminal is in electrical contact with the substrate, the other side of the first terminal is in contact with the cable, wherein the inverter housing includes a connector mounting portion which accommodate the body of the connector, sealing members seal a gap between the connector mounting portion and the connector.

Abstract: The present invention relates to a brushless motor, and an objective of the present invention is to provide a brushless motor which can significantly reduce the cogging torque and torque ripple of the motor by minimizing the rate of change of magnetoresistance in accordance with a change in position of a rotor through the optimization of the shape design of the rotor and a stator, and can also reduce the weight of the brushless motor through the optimization of the shape design taking into consideration the materials of the rotor and the stator.

Abstract: The present invention relates to a BLDC motor integrated with an inverter, having a motor and an inverter part that are integrally formed, and to a BLDC motor integrated with an inverter, having an improved arrangement of switching elements mounted on a PCB substrate of an inverter part and three phase terminals of a stator coil such that the inverter part including the PCB substrate can be compactly formed.

Abstract: The present invention relates to a brushless motor, and an objective of the present invention is to provide a brushless motor which can significantly reduce the cogging torque and torque ripple of the motor by minimizing the rate of change of magnetoresistance in accordance with a change in position of a rotor through the optimization of the shape design of the rotor and a stator, and can also reduce the weight of the brushless motor through the optimization of the shape design taking into consideration the materials of the rotor and the stator.

Abstract: A display device and a method of manufacturing a display device are disclosed. In one aspect, the display devices includes display area configured to display an image, a non-display area adjacent to the display area, and a first substrate having a first side and including a touch sensor in the display area and a touch sensor pad in the non-display area. The display device also includes a second substrate opposite to the first substrate, the second substrate including a pixel in the display area and a connecting pad in the non-display area, and a conductive member configured to electrically connect the touch sensor pad and the connecting pad. An inter-bar is interposed between the first and second substrates and between the first side of the first substrate and the touch sensor pad.