Abstract: A circuit includes local computing cells. Each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a first data type, a first sum including (i) a first product of a first input data element and a first weight data element; and (ii) a second product of a second input data element and a second weight data element. Each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a second data type, (i) a second sum of a first portion of a third input data element and a first portion of a third weight data element; and (ii) a third product of a second portion of the third input data element and a second portion of the third weight data element.

Abstract: A control system for a wafer transport vehicle is provided. The control system includes a control apparatus, a database, an onboard interface of the wafer transport vehicle and an operation control center. The control apparatus is arranged in a container of the wafer transport vehicle and configured to detect a environmental parameters in a container of the wafer transport vehicle and regulate the internal environment of a container of the wafer transport vehicle. The database is in communication with the control apparatus and configured store the environmental parameters detected by the control apparatus. The onboard interface is in communication with the control apparatus and configured to remotely control the control apparatus. The operation control center is in communication with the control apparatus and the onboard interface of the wafer transport vehicle and configured to receive the environmental parameters detected by the control apparatus.

Abstract: A hybrid structure for computing-in-memory applications includes a memory cell and a digital-analog-hybrid local computing cell. The memory cell stores a weight. The digital-analog-hybrid local computing cell has a plurality of input lines, a digital output line and an analog output line. The input lines are configured to transmit a plurality of multi-bit input values. The digital-analog-hybrid local computing cell includes a digital local computing cell and a voltage local computing cell. The digital local computing cell receives the weight and is configured to generate a digital output value on the digital output line according to a higher bit of the multi-bit input values multiplied by the weight. The voltage local computing cell receives the weight and is configured to generate an analog output value on the analog output line according to a lower bit of the multi-bit input values multiplied by the weight.

Abstract: A floating point pre-alignment structure for computing-in-memory applications includes a time domain exponent computing block and an input mantissa pre-align block. The time domain exponent computing block is configured to compute a plurality of original input exponents and a plurality of original weight exponents to generate a plurality of flags. Each of the flags is determined by adding one of the original input exponents and one of the original weight exponents. The input mantissa pre-align block is configured to receive a plurality of original input mantissas and shift the original input mantissas according to the flags to generate a plurality of weighted input mantissas, and sparsity of the weighted input mantissas is greater than sparsity of the original input mantissas. Each of the flags has a negative correlation with a sum of the one of the original input exponents and the one of the original weight exponents.

Abstract: A dynamic differential-reference time-to-digital converter for computing-in-memory applications is controlled by a bias reference and a predetermined setting parameter, and includes a configurable main-reference selector and a plurality of time-to-digital converters. The configurable main-reference selector is configured to receive a plurality of edge-output signals, select one of the edge-output signals as a main reference and select others of the edge-output signals as a plurality of edge selected signals according to the predetermined setting parameter. One of the time-to-digital converters is configured to compare the bias reference with the main reference to output a bias multiplication-and-accumulation value, and others of the time-to-digital converters are configured to compare the main reference with the edge selected signals to output a plurality of differential multiplication-and-accumulation values.