Abstract: Method and system for automatically checking a circuit layout of a PCB are disclosed. The method includes acquiring routing constraint information in an automatic table format, converting the routing constraint information from the automatic table format into a readable table format and generating routing constraint information in the readable table format, inputting the routing constraint information in the readable table format into a PCB layout software in a plug-in manner for the PCB layout software to acquire a corresponding circuit routing rule, acquiring, after routing ends, a data file outputted by the PCB layout software, and generating a check report by comparing and checking the data file and the routing constraint information. With the method, the constraint information is automatically inputted into the PCB layout software, and a check report is automatically generated for correcting errors on a circuit layout in the layout software, to improve circuit layout efficiency.

Abstract: A hybrid structure for computing-in-memory applications includes a memory cell and a digital-analog-hybrid local computing cell. The memory cell stores a weight. The digital-analog-hybrid local computing cell has a plurality of input lines, a digital output line and an analog output line. The input lines are configured to transmit a plurality of multi-bit input values. The digital-analog-hybrid local computing cell includes a digital local computing cell and a voltage local computing cell. The digital local computing cell receives the weight and is configured to generate a digital output value on the digital output line according to a higher bit of the multi-bit input values multiplied by the weight. The voltage local computing cell receives the weight and is configured to generate an analog output value on the analog output line according to a lower bit of the multi-bit input values multiplied by the weight.

Abstract: A floating point pre-alignment structure for computing-in-memory applications includes a time domain exponent computing block and an input mantissa pre-align block. The time domain exponent computing block is configured to compute a plurality of original input exponents and a plurality of original weight exponents to generate a plurality of flags. Each of the flags is determined by adding one of the original input exponents and one of the original weight exponents. The input mantissa pre-align block is configured to receive a plurality of original input mantissas and shift the original input mantissas according to the flags to generate a plurality of weighted input mantissas, and sparsity of the weighted input mantissas is greater than sparsity of the original input mantissas. Each of the flags has a negative correlation with a sum of the one of the original input exponents and the one of the original weight exponents.

Abstract: A dynamic differential-reference time-to-digital converter for computing-in-memory applications is controlled by a bias reference and a predetermined setting parameter, and includes a configurable main-reference selector and a plurality of time-to-digital converters. The configurable main-reference selector is configured to receive a plurality of edge-output signals, select one of the edge-output signals as a main reference and select others of the edge-output signals as a plurality of edge selected signals according to the predetermined setting parameter. One of the time-to-digital converters is configured to compare the bias reference with the main reference to output a bias multiplication-and-accumulation value, and others of the time-to-digital converters are configured to compare the main reference with the edge selected signals to output a plurality of differential multiplication-and-accumulation values.