Abstract: Disclosed is a method of identifying dementia by at least one processor of a device. The method includes performing a first task that causes a first object to be displayed on a first region of a screen displayed on a user terminal; and when a preset condition is satisfied, performing a second task that causes at least one object, which induces the user's gaze, to be displayed instead of the first object on the screen of the user terminal.

Abstract: A method of identifying dementia is disclosed that includes causing a user terminal to display an N-th screen including a plurality of objects. The user terminal may further display an N+1-th screen with the objects rearranged at positions on the N+1-th screen which are different from positions of the objects included in the N-th screen when an N-th selection input of selecting any one from among the objects included in the N-th screen is received. When an N+1-th selection input for selecting any one from among the objects included in the N+1-th screen is received, a third task of determining whether an answer of the N+1-th selection input is correct is performed based on whether the object selected from the N+1-th selection input is the same as at least one object selected from at least one previous selection input including the N-th selection input.

Abstract: Embodiments of the present disclosure generally relate to a multilayer stack used as a mask in extreme ultraviolet (EUV) lithography and methods for forming a multilayer stack. In one embodiment, the method includes forming a carbon layer over a film stack, forming a metal rich oxide layer on the carbon layer by a physical vapor deposition (PVD) process, forming a metal oxide photoresist layer on the metal rich oxide layer, and patterning the metal oxide photoresist layer. The metal oxide photoresist layer is different from the metal rich oxide layer and is formed by a process different from the PVD process. The metal rich oxide layer formed by the PVD process improves adhesion of the metal oxide photoresist layer and increases the secondary electrons during EUV lithography, which leads to decreased EUV dose energies.

Abstract: Embodiments of the present disclosure generally relate to methods for enhancing photoresist (PR) to have improved profile control. A method for treating a PR includes positioning a workpiece within a process region of a processing chamber, where the workpiece contains a patterned PR disposed on an underlayer, and treating the patterned PR by exposing the workpiece to a sequential infiltration synthesis (SIS) process to produce a treated patterned PR which is denser and harder than the patterned PR. The SIS process includes one or more infiltration cycles of exposing the patterned PR to a precursor containing silicon or boron, infiltrating the patterned PR with the precursor, purging to remove remnants of the precursor, exposing the patterned PR to an oxidizing agent, infiltrating the patterned PR with the oxidizing agent to produce oxide coating disposed on inner surfaces of the patterned PR, and purging to remove remnants of the oxidizing agent.

Abstract: Methods for formation of a layer stack during a back-end-of-line (BEOL) process flow and the layer stack formed therefrom are provided. In one or more embodiments, the method utilizes a two-dimensional (2D) self-aligned scheme with a subtractive metal etch. The method includes using a hard mask to form a via with a small width which is formed through or contacts each of a first metal layer and a second metal layer. The via is filled with a metal gapfill to connect the first metal layer and the second metal layer. Each of the first metal layer and the second metal layer are patterned to form a plurality of features.

Abstract: Embodiments of the present disclosure generally relate to a multilayer stack used as a mask in extreme ultraviolet (EUV) lithography and methods for forming a multilayer stack. In one embodiment, the method includes forming a carbon layer over a film stack, forming a metal rich oxide layer on the carbon layer by a physical vapor deposition (PVD) process, forming a metal oxide photoresist layer on the metal rich oxide layer, and patterning the metal oxide photoresist layer. The metal oxide photoresist layer is different from the metal rich oxide layer and is formed by a process different from the PVD process. The metal rich oxide layer formed by the PVD process improves adhesion of the metal oxide photoresist layer and increases the secondary electrons during EUV lithography, which leads to decreased EUV dose energies.

Abstract: Embodiments of the present disclosure generally relate to methods for etching materials. In one or more embodiments, the method includes positioning a substrate in a process volume of a process chamber, where the substrate includes a metallic ruthenium layer disposed thereon, and exposing the metallic ruthenium layer to an oxygen plasma to produce a solid ruthenium oxide on the metallic ruthenium layer and a gaseous ruthenium oxide within the process volume. The method also includes exposing the solid ruthenium oxide to a secondary plasma to convert the solid ruthenium oxide to either metallic ruthenium or a ruthenium oxychloride compound. The metallic ruthenium is in a solid state on the metallic ruthenium layer or the ruthenium oxychloride compound is in a gaseous state within the process volume.

Abstract: A method and apparatus for patterning semiconductor materials using tin-based materials as mandrels, hardmasks, and liner materials are provided. One or more implementations of the present disclosure use tin-oxide and/or tin-carbide materials as hardmask materials, mandrel materials, and/or liner material during various patterning applications. Tin-oxide or tin-carbide materials are easy to strip relative to other high selectivity materials like metal oxides (e.g., TiO2, ZrO2, HfO2, Al2O3) to avoid influencing critical dimensions and generate defects. In addition, tin-oxide and tin-carbide have low refractive index, k-value, and are transparent under 663-nm for lithography overlay.

Abstract: Embodiments of the present disclosure generally relate to a multilayer stack used as a mask in extreme ultraviolet (EUV) lithography and methods for forming a multilayer stack. In one embodiment, the method includes forming a carbon layer over a film stack, forming a metal rich oxide layer on the carbon layer by a physical vapor deposition (PVD) process, forming a metal oxide photoresist layer on the metal rich oxide layer, and patterning the metal oxide photoresist layer. The metal oxide photoresist layer is different from the metal rich oxide layer and is formed by a process different from the PVD process. The metal rich oxide layer formed by the PVD process improves adhesion of the metal oxide photoresist layer and increases the secondary electrons during EUV lithography, which leads to decreased EUV dose energies.

Abstract: Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively recessing a first metal on a semiconductor substrate with respect to an exposed first dielectric material. The methods may include forming a liner over the recessed first metal and the exposed first dielectric material. The methods may include forming a second dielectric material over the liner. The methods may include forming a hard mask over selected regions of the second dielectric material. The methods may also include selectively removing the second dielectric material to expose a portion of the liner overlying the recessed first metal.

Abstract: Methods and apparatus to form fully self-aligned vias are described. Portions of first conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed portions of the first conductive lines and pillars are formed from the first metal film. A second insulating layer is deposited around the pillars. The pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.

Abstract: Methods and apparatus to form fully self-aligned vias are described. First conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed first conductive lines and pillars are formed from the first metal film. Some of the pillars are selectively removed and a second insulating layer is deposited around the remaining pillar. The remaining pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.

Abstract: A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.

Abstract: A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.

Abstract: A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.

Abstract: Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide, silicon nitride, aluminum oxide or zirconium oxide are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications.

Abstract: Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively recessing a first metal on a semiconductor substrate with respect to an exposed first dielectric material. The methods may include forming a liner over the recessed first metal and the exposed first dielectric material. The methods may include forming a second dielectric material over the liner. The methods may include forming a hard mask over selected regions of the second dielectric material. The methods may also include selectively removing the second dielectric material to expose a portion of the liner overlying the recessed first metal.

Abstract: Methods and apparatus to form fully self-aligned vias are described. A seed gapfill layer is formed on a recessed first insulating layers positioned between first conductive lines. Pillars are formed from the seed gapfill layer and a second insulating layer is deposited in the gaps between pillars. The pillars are removed and a third insulating layer is deposited in the gaps in the second insulating layer to form an overburden of third insulating layer. A portion of the overburden of the third insulating layer is removed to expose the first conductive lines and form vias.

Abstract: Methods and apparatus to form fully self-aligned vias are described. Portions of first conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed portions of the first conductive lines and pillars are formed from the first metal film. A second insulating layer is deposited around the pillars. The pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.

Abstract: Methods of forming semiconductor devices comprising etching a hardmask and spin-on-carbon layer through an opening in a photoresist to expose a gapfill material. The photoresist, spin-on-carbon layer and gapfill material are removed. A new spin-on-carbon layer, hardmask and photoresist are formed with an opening over a spacer mandrel. The hardmask, spin-on-carbon layer are etched through the opening and the layers and spacer mandrel are removed. An etch stop layer and oxide layer are removed and a height of the spacer mandrel and gapfill material are reduced exposing portions of the substrate. The exposed portions of the substrate are fin etched and the layers removed.