Abstract: Numerous examples are disclosed of systems and methods for operating one or more arrays of resistive random access memory (RRAM) cells. In one example, a read bias generator comprises a bias transistor, a feedback loop, a replica resistor, and a reference unit. Optionally, the read bias generator is coupled to an array of RRAM units.

Abstract: In one example, a method comprises determining a bias voltage in response to a change in operating temperature of an array of non-volatile memory cells, each of the non-volatile memory cells in the array of memory cells comprising a control gate terminal and an erase gate terminal; and applying the bias voltage to a control gate terminal and an erase gate terminal of a selected memory cell in the array of memory cells while reading the selected memory cell.

Abstract: In one example, a system comprises an array of non-volatile memory cells arranged in rows and columns, wherein each non-volatile memory cell comprises a word line terminal and a bit line terminal; and a row circuit to receive a row address and a bias voltage and to output the bias voltage when the row address corresponds to a row of the array associated with the row circuit, wherein the bias voltage is provided to terminals of non-volatile memory cells in the row of the array associated with the row circuit.

Abstract: In one example, a system comprises an array of memory cells arranged in rows and columns, the array comprising bitlines coupled to respective columns in the array, respective bitlines comprising a sensing bitline metal layer and a current-carrying metal layer, wherein the sensing bitline metal layer does not carry current.

Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising an array of non-volatile memory cells arranged in rows and columns; and a sigma-delta analog-to-digital converter to receive a current from a column of the vector-by-matrix multiplication array and to generate a digital output in response to the current.

Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an output block coupled to the vector-by-matrix multiplication array to receive current from the columns of the array, the output block comprising a current-to-voltage converter to receive current from one or two columns and convert the current into a voltage, the current-to-voltage converter comprising one or more variable resistors configurable to adjust the range of the voltage; and an analog-to-digital converter to convert the voltage into digital bits.

Abstract: In one example, a circuit comprises a current-to-voltage converter to convert a first current into a first voltage and to convert a second current into a second voltage, where the first current and the second current are differential currents; a level shifter to convert the first voltage into a third voltage and to convert the second voltage into a fourth voltage; and an analog-to-digital converter to convert the third voltage and the fourth voltage into a set of output bits.

Abstract: In one example, a system comprises a bitline regulation circuit comprising a first set of switches coupled to a bitline; and a second set of switches coupled to the bitline; wherein the bitline regulation circuit receives a first input from the first set of switches and a second input from the second set of switches, the first input comprising voltage and current and the second input comprising voltage and no current.

Abstract: In one example, a system comprises a current-to-voltage converter to generate differential voltages from differential currents comprising a first current and a second current, the current-to-voltage converter comprising: a first bitline to provide the first current; a second bitline to provide the second current; a first regulator to apply a first voltage to the first bitline; a second regulator to apply a second voltage to the second bitline; a regulating circuit comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first output terminal and the second output terminal providing the differential voltages; and a common mode circuit.

Abstract: In one example, a system comprises an array of resistive random access memory (RRAM) units arranged in rows and columns; and a sense amplifier for determining a differential value stored in a first RRAM unit and a second RRAM unit in the array.

Abstract: In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, the array comprising a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells; and an output block coupled to the array, the output block comprising: a current-to-voltage converter to convert a first current on the first bit line into a first voltage and to convert a second current on the second bit line into a second voltage; and an analog-to-digital converter to convert one or more of the first voltage and the second voltage into a set of output bits.

Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising an array of non-volatile memory cells arranged in rows and columns; and a sigma-delta analog-to-digital converter to receive a current from a column of the vector-by-matrix multiplication array and to generate a digital output in response to the current.

Abstract: According to an aspect described herein, a device is proposed for electronically driving an LED comprising a data signal line, a threshold signal line, and a select signal line. Further provided is an LED electrically connected in series with a dual-gate transistor and together therewith between first and second potential terminals. A first control gate of the dual gate transistor is connected to the threshold line. The device also includes a select latch circuit comprising a charge latch connected to a second control gate of the dual gate transistor and to a current line contact of the dual gate transistor, and a control transistor comprising a control terminal connected to the select signal line.

Abstract: Numerous examples are disclosed of input blocks for an array of non-volatile memory cells and associated methods. In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an input block comprising a plurality of row circuits and a global digital-to-analog converter generator to generate 2m different analog voltages, where m is an integer; wherein the row circuits in the plurality of row circuits respectively apply one of the 2m different analog voltages to an associated row in the array.

Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns, a first set of columns storing W+ weights and a second set of columns storing W? weights; and an output circuit to receive a first current from a respective column in the first set of columns and a second current from a respective column in the second set of columns and to generate a first voltage and a second voltage, the output circuit comprising a first current-to-voltage converter comprising a first integration capacitor to provide the first voltage equal to an initial voltage minus a first discharge value due to the first current, and a second current-to-voltage converter comprising a second integration capacitor to provide the second voltage equal to the initial voltage minus a second discharge value due to the second current.

Abstract: The invention relates to various aspects of a ?-LED or a ?-LED array for augmented reality or lighting applications, in particular in the automotive field. The ?-LED is characterized by particularly small dimensions in the range of a few ?m.

Abstract: Disclosed are various aspects of a ?-LED or a ?-LED array for augmented reality or lighting applications, in particular in the automotive field. The ?-LED is characterized by particularly small dimensions in the range of a few ?m.

Abstract: Disclosed are various aspects of a ?-LED or a ?-LED array for augmented reality or lighting applications, in particular in the automotive field. The ?-LED is characterized by particularly small dimensions in the range of a few ?m.

Abstract: Numerous examples are disclosed of a masking circuit for inputs and outputs in a neural network array. In one example, a system comprises a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent an application of a sparse input to one or more rows in the array when a condition is satisfied.

Abstract: In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, the array comprising a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells; and an output block coupled to the array, the output block comprising: a current-to-voltage converter to convert a first current on the first bit line into a first voltage and to convert a second current on the second bit line into a second voltage; and an analog-to-digital converter to convert one or more of the first voltage and the second voltage into a set of output bits.