Abstract: An on-board system for location estimation and communication for a vehicle. In some embodiments, the on-board system includes a global navigation satellite system receiver, an inertial sensing system, a wireless receiver, and a processing circuit. The wireless receiver includes at least one of a cellular communications receiver, and a wireless local area networking receiver.

Abstract: A device reorders first cells of a first conversation; determines whether a reorder window size is exceeded a first time based on the first conversation; subjects the first conversation to a fast time out when the reorder window size is exceeded the first time; reorders second cells of a second conversation while subjecting the first conversation to the fast time out; prepares a packet based on the first conversation; and transmits the packet to a PFE of another device.

Abstract: A device comprises a plurality of interface circuits configured for communicating between a semantic processing unit and a memory and a selection circuit for selecting an interface circuit allocated to a semantic processing unit for processing a data operation request in the memory.

Abstract: A device performs lookup functions for a semantic processing unit. The device comprises a plurality of interface circuits for receiving data operation requests from the semantic processing unit. The device comprises a buffer for allocating an interface circuit to a semantic processing unit having a data operation request. A selection circuit, coupled between the plurality of interface circuits and a memory unit, selects an allocated circuit for accessing the memory unit to process the data operation request.

Abstract: A device comprises a plurality of interface circuits for communicating between a semantic processor and a memory. Each interface circuit is configured for receiving lookup requests from the semantic processor. The device further comprises a buffer for allocating an interface circuit, if available, to the semantic processor. The allocated interface circuit is selected to access the memory for processing the lookup request.

Abstract: A memory subsystem includes multiple different caches configured for different types of data transfer operations between one or more processing units and a main memory. The different caches can include a first general cache configured for general random memory accesses, a software controlled cache used for controlling cache operations for different processing devices accessing the same data, and a streaming cache configured for large packet data memory accesses. An arbiter may be used for arbitrating requests by the multiple different caches for accessing the main memory.