Patents by Inventor Hoai V. Tran

Hoai V. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Arbiter for array machine context data memory
    Patent number: 7451268
    Abstract: A device comprises a plurality of interface circuits configured for communicating between a semantic processing unit and a memory and a selection circuit for selecting an interface circuit allocated to a semantic processing unit for processing a data operation request in the memory.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: November 11, 2008
    Assignee: Gigafin Networks, Inc.
    Inventors: Somsubhra Sikdar, Kevin Jerome Rowett, Hoai V. Tran, Jonathan Sweedler, Komal Rathi, Mike Davoudi
  • Array machine context data memory
    Patent number: 7424571
    Abstract: A device performs lookup functions for a semantic processing unit. The device comprises a plurality of interface circuits for receiving data operation requests from the semantic processing unit. The device comprises a buffer for allocating an interface circuit to a semantic processing unit having a data operation request. A selection circuit, coupled between the plurality of interface circuits and a memory unit, selects an allocated circuit for accessing the memory unit to process the data operation request.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: September 9, 2008
    Assignee: Gigafin Networks, Inc.
    Inventors: Somsubhra Sikdar, Kevin Jerome Rowett, Hoai V. Tran, Jonathan Sweedler, Komal Rathi, Mike Davoudi
  • Contextual memory interface for network processor
    Patent number: 7398356
    Abstract: A memory subsystem includes multiple different caches configured for different types of data transfer operations between one or more processing units and a main memory. The different caches can include a first general cache configured for general random memory accesses, a software controlled cache used for controlling cache operations for different processing devices accessing the same data, and a streaming cache configured for large packet data memory accesses. An arbiter may be used for arbitrating requests by the multiple different caches for accessing the main memory.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: July 8, 2008
    Assignee: Mistletoe Technologies, Inc.
    Inventors: Hoai V. Tran, Kevin Jerome Rowett, Somsubhra Sikdar, Jonathan Sweedler, Caveh Jalali