Abstract: A system for transporting substrates and precisely align the substrates horizontally and vertically. The system decouples the functions of transporting the substrates, vertically aligning the substrates, and horizontally aligning the substrates. The transport system includes a carriage upon which plurality of chuck assemblies are loosely positioned, each of the chuck assemblies includes a base having vertical alignment wheels to place the substrate in precise vertical alignment. A pedestal is configured to freely slide on the base. The pedestal includes a set of horizontal alignment wheels that precisely align the pedestal in the horizontal direction. An electrostatic chuck is magnetically held to the pedestal.

Abstract: A cloud infrastructure diagnostics system comprises a cloud state configuration module operative to define a cloud state model with respect to a cloud infrastructure, wherein the cloud state model comprises a structured collection of selected operational characteristics relative to the cloud infrastructure components. The cloud state model may include a definition of dependencies between the cloud infrastructure components where applicable. A cloud state monitoring module is operative, responsive to the cloud state model definition, to collect periodic cloud state updates with respect to the cloud infrastructure. A cloud state analysis module is operative, responsive to receiving the periodic cloud state updates, to perform: comparing one or more cloud state updates to a corresponding predefined set of reference states; and determining one or more notifications to be transmitted with respect to the operational characteristics of the cloud infrastructure components.

Abstract: A cloud infrastructure diagnostics system comprises a cloud state configuration module operative to define a cloud state model with respect to a cloud infrastructure, wherein the cloud state model comprises a structured collection of selected operational characteristics relative to the cloud infrastructure components. The cloud state model may include a definition of dependencies between the cloud infrastructure components where applicable. A cloud state monitoring module is operative, responsive to the cloud state model definition, to collect periodic cloud state updates with respect to the cloud infrastructure. A cloud state analysis module is operative, responsive to receiving the periodic cloud state updates, to perform: comparing one or more cloud state updates to a corresponding predefined set of reference states; and determining one or more notifications to be transmitted with respect to the operational characteristics of the cloud infrastructure components.

Abstract: There is described apparatus and methods for transporting and processing substrates including wafers as to efficiently produce at reasonable costs improved throughput as compared to systems in use today. A linear transport chamber includes linear tracks and robot arms riding on the linear tracks to linearly transfer substrates along the sides of processing chambers for feeding substrates into a controlled atmosphere through a load lock and then along a transport chamber as a way of reaching processing chambers. A four-axis robot arm is disclosed, capable of linear translation, rotation and articulation, and z-motion.

Abstract: A system for transporting substrates and precisely align the substrates horizontally and vertically. The system decouples the functions of transporting the substrates, vertically aligning the substrates, and horizontally aligning the substrates. The transport system includes a carriage upon which plurality of chuck assemblies are loosely positioned, each of the chuck assemblies includes a base having vertical alignment wheels to place the substrate in precise vertical alignment. A pedestal is configured to freely slide on the base. The pedestal includes a set of horizontal alignment wheels that precisely align the pedestal in the horizontal direction. An electrostatic chuck is magnetically held to the pedestal.

Abstract: There is described apparatus and methods for transporting and processing substrates including wafers as to efficiently produce at reasonable costs improved throughput as compared to systems in use today. A linear transport chamber includes linear tracks and robot arms riding on the linear tracks to linearly transfer substrates along the sides of processing chambers for feeding substrates into a controlled atmosphere through a load lock and then along a transport chamber as a way of reaching processing chambers. A four-axis robot arm is disclosed, capable of linear translation, rotation and articulation, and z-motion.

Abstract: There is described apparatus and methods for transporting and processing substrates including wafers as to efficiently produce at reasonable costs improved throughput as compared to systems in use today. A linear transport chamber includes linear tracks and robot arms riding on the linear tracks to linearly transfer substrates along the sides of processing chambers for feeding substrates into a controlled atmosphere through a load lock and then along a transport chamber as a way of reaching processing chambers. A four-axis robot arm is disclosed, capable of linear translation, rotation and articulation, and z-motion.

Abstract: There is described apparatus and methods for transporting and processing substrates including wafers as to efficiently produce at reasonable costs improved throughput as compared to systems in use today. A linear transport chamber includes linear tracks and robot arms riding on the linear tracks to linearly transfer substrates along the sides of processing chambers for feeding substrates into a controlled atmosphere through a load lock and then along a transport chamber as a way of reaching processing chambers. A four-axis robot arm is disclosed, capable of linear translation, rotation and articulation, and z-motion.

Abstract: There is described apparatus and methods for transporting and processing substrates including wafers as to efficiently produce at reasonable costs improved throughput as compared to systems in use today. A linear transport chamber includes linear tracks and robot arms riding on the linear tracks to linearly transfer substrates along the sides of processing chambers for feeding substrates into a controlled atmosphere through a load lock and then along a transport chamber as a way of reaching processing chambers. A four-axis robot arm is disclosed, capable of linear translation, rotation and articulation, and z-motion.

Abstract: There is described apparatus and methods for transporting and processing substrates including wafers as to efficiently produce at reasonable costs improved throughput as compared to systems in use today. A linear transport chamber includes linear tracks and robot arms riding on the linear tracks to linearly transfer substrates along the sides of processing chambers for feeding substrates into a controlled atmosphere through a load lock and then along a transport chamber as a way of reaching processing chambers. A four-axis robot arm is disclosed, capable of linear translation, rotation and articulation, and z-motion.

Abstract: Aspects of the method and system for rejecting single sided leakage into an amplitude modulated channel may comprise an AM demodulator for demodulating a received composite broadcast signal's control channel to generate an amplitude modulated (AM) component. A PM demodulator may demodulate a received composite broadcast signal's control channel to generate a phase modulated (PM) component. At least one subtractor may subtract an AM leakage component and a PM leakage component contributed by the single sided leakage in the received composite broadcast signal's control channel. The system may comprise at least one of each of AM and PM bandpass filters and envelope detectors that filter and detect envelopes of the AM and PM components at 982.5 Hz and 922.5 Hz.

Abstract: An analysis unit receives a sample of request data sent from a browser to a Web application. The browser and the Web application communicate data using HTTP protocol. The Web application receives the request data using GET method or POST method. The analysis unit analyzes a rule of HTTP protocol based on the sample. The rule includes a number of the request data, a name of the request data, and a format of response data corresponding to the request data. A generation unit generates a protocol converter to connect a communication of a Web service with a communication of the Web application based on the rule.

Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.

Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.

Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.

Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.

Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.