Patents by Inventor Hoang Q. Dao

Hoang Q. Dao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9837398
    Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: December 5, 2017
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Omid Rowhani, Jason P. Cain, Ioan Cordos, Michael Davinson Sherriff, Hoang Q. Dao
  • Patent number: 7131055
    Abstract: A Viterbi decoder includes an ACS unit that performs state metric updates for every symbol cycle. State metric updates involve adding the state metrics corresponding to a likely input symbol to the respective branch matrix, comparing the results of the additions to determine which is smaller, and selecting the smaller result for the next state metric. The ACS unit includes two parallel adders followed by a parallel comparator that generates a multiplexer-select signal. The outputs of the parallel adders are input into a multiplexer and the multiplexer-select signal is input into the multiplexer for a decision.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventors: Sanu K. Mathew, Ram Krishnamurthy, Hoang Q. Dao
  • Publication number: 20040177304
    Abstract: A Viterbi decoder includes an ACS unit that performs state metric updates for every symbol cycle. State metric updates involve adding the state metrics corresponding to a likely input symbol to the respective branch matrix, comparing the results of the additions to determine which is smaller, and selecting the smaller result for the next state metric. The ACS unit includes two parallel adders followed by a parallel comparator that generates a multiplexer-select signal. The outputs of the parallel adders are input into a multiplexer and the multiplexer-select signal is input into the multiplexer for a decision.
    Type: Application
    Filed: February 25, 2003
    Publication date: September 9, 2004
    Applicant: Intel Corporation
    Inventors: Sanu K. Mathew, Ram Krishnamurthy, Hoang Q. Dao