Abstract: A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.

Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Abstract: A method for producing a layer stack includes providing a tungsten layer, depositing an oxidation barrier layer that immunizes the tungsten layer against oxidation on top of the tungsten layer, and depositing a cap layer on top of the oxidation barrier layer. An integrated circuit is also described.

Abstract: One possible embodiment is a method for manufacturing a structure on a substrate which can be used in the manufacturing of a semiconductor device, including the steps of: forming a first structure on the substrate having at least one sidewall, forming at least one layer as a second structure selectively on the at least one sidewall of the first structure by an epitaxial technique, electroplating, selective silicon dioxide deposition, selective low pressure CVD or an atomic layer deposition technique. Furthermore semiconductor devices, uses of equipment and structures are covered.

Abstract: Polysilicon regions are formed by performing a thermal treatment in a hydrogen ambient environment after patterning a polysilicon structure.

Abstract: A semiconductor structure includes first and second conductive lines which cross each other. The second conductive lines are electrically insulated from the first conductive lines via an insulating material. The second conductive lines include first and second sections. First sections are arranged beneath crossing first conductive lines and include a semiconductor material. The second sections are disposed between adjacent first conductive lines and include a metal-semiconductor compound. A method of manufacturing a semiconductor structure involves forming initial second conductive lines, forming first conductive lines and providing a metal-semiconductor compound on an exposed surface of the initial second conductive lines, thereby obtaining second conductive lines. Forming the metal-semiconductor compound is performed after forming the first conductive lines.

Abstract: A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.

Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Abstract: A semiconductor product (1) includes a plurality of wordlines extending along a first lateral direction (x) along a substrate surface (22) and also includes contact structures (3) as well as filling structures (4) therebetween. Along the first direction (x) the contact structures (3) and the filling structures (4) are arranged in alternating order between two respective wordlines. Each contact structure (3) serves to connect two active areas (23) separated by one respective trench isolation filling (24) to a respective bitline (14). Accordingly, the width of the first contact structures (3) is much larger than the width of the bitlines (14) along the first direction (x). According to embodiments of the invention, tapered upper portions (9) of the contact structures (3) are shaped, the upper portions (9) having a width being significantly smaller than the width of the contact structures (3) along the first direction (x).

Abstract: Dielectric gratings are formed between the word line stacks. Spacers are applied to the sidewalls of the word line stacks and the dielectric gratings. In the openings between the spacers, silicon is epitaxially grown on the upper surfaces of source/drain regions, which are implanted self-aligned to the word line stacks. A silicide is formed on the grown silicon, and a metal layer is applied and structured to form local interconnects, which connect the source/drain regions to upper bit lines.