Abstract: Various embodiments may provide an electronic synapse device. The electronic synapse device may include a body including a doped chalcogenide layer including a chalcogenide material and a dopant. The electronic synapse device may also include a drain electrode in contact with the body. The electronic synapse device may further include a source electrode in contact with the body. The electronic synapse device may additionally include a gate electrode including an electrode contact layer in contact with the doped chalcogenide layer. The electrode contact layer may be any one selected from a group consisting of an electrically conductive layer including an electrically conductive material and a dopant layer including the dopant.

Abstract: An elastic gear First-In-First-Out (FIFO) buffer architecture is disclosed. The proposed elastic gear FIFO buffer uses a frequency monitor unit to control clock frequency compensation. By using an independent frequency monitor unit, the data latency and FIFO buffer size are best optimized. An elastic gear FIFO could be utilized in applications where clock compensation and asynchronous data width conversion are desired or required.

Abstract: An elastic gear First-In-First-Out (FIFO) buffer architecture is disclosed. The proposed elastic gear FIFO buffer uses a frequency monitor unit to control clock frequency compensation. By using an independent frequency monitor unit, the data latency and FIFO buffer size are best optimized. An elastic gear FIFO could be utilized in applications where clock compensation and asynchronous data width conversion are desired or required.

Abstract: A microcontroller employs an asynchronous serial port for predictably updating a baud divisor during data reception. A write enable to the baud counter ensures that the current value of the baud count in the baud counter is greater than a predetermined number of clocks so that the working baud divisor to be loaded from the working baud divisor register is stabilized. The working baud divisor register is updated during data reception by the serial port by a software write to a visible baud divisor register provided the working baud divisor in the working baud divisor register is not being used to load the baud counter. A working baud divisor register thereby maintains a value guaranteed to be stable by the time a baud counter needs to be reloaded. A visible baud divisor register and the baud counter can be on different, possibly asynchronous clocks.