Abstract: Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used.

Abstract: Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used.

Abstract: Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used.

Abstract: A non-volatile storage device in which current sensing is performed for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.

Abstract: A non-volatile storage device in which current sensing is performed for a non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.

Abstract: Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used.

Abstract: Current sensing is performed in a non-volatile storage device for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.

Abstract: Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.

Abstract: A non-volatile storage device in which current sensing is performed for a non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.

Abstract: Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.

Abstract: A non-volatile storage device in which current sensing is performed for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.

Abstract: Current sensing is performed in a non-volatile storage device for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.

Abstract: Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.

Abstract: A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector.

Abstract: A content addressable memory cell may include a non-volatile memory storage transistor coupled to an enhancement transistor. In some embodiments, the enhancement transistor may be a select cell. In some embodiments, the storage transistor may use substrate hot electron injection. Through the use of the enhancement transistor, overerasing and read disturb problems may be mitigated.

Abstract: Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.

Abstract: A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector.