Abstract: An electronic device comprising a semiconductor memory unit that may include a variable resistance element configured to be changed in a resistance value thereof in response to current flowing through both ends thereof, a toggle data generation unit configured to generate toggle data of which logic value toggles with a predetermined cycle, in a first mode for testing reliability of the variable resistance element, a data transfer line configured to transfer data inputted from an outside, and a driving unit configured to flow current which is changed in its direction with the predetermined cycle, through the variable resistance element in response to the toggle data in the first mode, and flow current through the variable resistance element in a direction determined in response to the data of the data transfer line, in a second mode in writing date into or reading data from the variable resistance element.

Abstract: An electronic device comprising a semiconductor memory unit that may include a variable resistance element configured to be changed in a resistance value thereof in response to current flowing through both ends thereof, a toggle data generation unit configured to generate toggle data of which logic value toggles with a predetermined cycle, in a first mode for testing reliability of the variable resistance element, a data transfer line configured to transfer data inputted from an outside, and a driving unit configured to flow current which is changed in its direction with the predetermined cycle, through the variable resistance element in response to the toggle data in the first mode, and flow current through the variable resistance element in a direction determined in response to the data of the data transfer line, in a second mode in writing date into or reading data from the variable resistance element.

Abstract: An electronic device comprising a semiconductor memory unit that may include a variable resistance element configured to be changed in a resistance value thereof in response to current flowing through both ends thereof, a toggle data generation unit configured to generate toggle data of which logic value toggles with a predetermined cycle, in a first mode for testing reliability of the variable resistance element, a data transfer line configured to transfer data inputted from an outside, and a driving unit configured to flow current which is changed in its direction with the predetermined cycle, through the variable resistance element in response to the toggle data in the first mode, and flow current through the variable resistance element in a direction determined in response to the data of the data transfer line, in a second mode in writing date into or reading data from the variable resistance element.

Abstract: An electronic device comprising a semiconductor memory unit that may include a variable resistance element configured to be changed in a resistance value thereof in response to current flowing through both ends thereof, a toggle data generation unit configured to generate toggle data of which logic value toggles with a predetermined cycle, in a first mode for testing reliability of the variable resistance element, a data transfer line configured to transfer data inputted from an outside, and a driving unit configured to flow current which is changed in its direction with the predetermined cycle, through the variable resistance element in response to the toggle data in the first mode, and flow current through the variable resistance element in a direction determined in response to the data of the data transfer line, in a second mode in writing date into or reading data from the variable resistance element.

Abstract: An input latch circuit of a semiconductor device includes a setup time adjusting unit configured to selectively delay a clock signal and a hold time adjusting unit configured to selectively delay an input signal. The input latch circuit also includes a latch unit configured to latch an output signal of the hold time adjusting unit according to an output signal of the setup time adjusting unit. The input latch circuit changes and delays the clock signal and the input signal by cutting a fuse within the setup time adjusting unit and the hold time adjusting unit without requiring a change to a circuit in order to adjust a setup time and a hold time.

Abstract: An input latch circuit of a semiconductor device includes a setup time adjusting unit configured to selectively delay a clock signal and a hold time adjusting unit configured to selectively delay an input signal. The input latch circuit also includes a latch unit configured to latch an output signal of the hold time adjusting unit according to an output signal of the setup time adjusting unit. The input latch circuit changes and delays the clock signal and the input signal by cutting a fuse within the setup time adjusting unit and the hold time adjusting unit without requiring a change to a circuit in order to adjust a setup time and a hold time.