Patents by Inventor Hoe-Min JEONG

Hoe-Min JEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230403855
    Abstract: A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.
    Type: Application
    Filed: August 9, 2023
    Publication date: December 14, 2023
    Applicant: SK hynix Inc.
    Inventors: In-Su PARK, Jong-Gi KIM, Hai-Won KIM, Hoe-Min JEONG
  • Publication number: 20230378206
    Abstract: Disclosed is an image sensor including a substrate having a photoelectric conversion element disposed therein a passivation layer disposed on the substrate and extending in a first direction, a conductive pattern disposed on the passivation layer, and an adhesive layer deposited on the passivation layer and the conductive pattern, wherein the conductive pattern includes a first flat area disposed on the passivation layer and extending in the first direction, and an inclined area connected to the first flat area, wherein a first top face of the inclined area is bent from a second top face of the first flat area, wherein the first top face has a constant slope with respect to the second top face.
    Type: Application
    Filed: March 22, 2023
    Publication date: November 23, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Su PARK, Seung Joo NAH, Hoe Min JEONG, Hee Geun JEONG
  • Patent number: 11751395
    Abstract: A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: September 5, 2023
    Assignee: SK hynix Inc.
    Inventors: In-Su Park, Jong-Gi Kim, Hai-Won Kim, Hoe-Min Jeong
  • Publication number: 20220123020
    Abstract: A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 21, 2022
    Applicant: SK hynix Inc.
    Inventors: In-Su PARK, Jong-Gi KIM, Hai-Won KIM, Hoe-Min JEONG
  • Patent number: 11244956
    Abstract: A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: February 8, 2022
    Assignee: SK hynix Inc.
    Inventors: In-Su Park, Jong-Gi Kim, Hai-Won Kim, Hoe-Min Jeong
  • Publication number: 20200328226
    Abstract: A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.
    Type: Application
    Filed: November 11, 2019
    Publication date: October 15, 2020
    Applicant: SK hynix Inc.
    Inventors: In-Su PARK, Jong-Gi KIM, Hai-Won KIM, Hoe-Min JEONG