Patents by Inventor Hoe-Sam Jeong

Hoe-Sam Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11032505
    Abstract: Provided are devices having a device including a ramp signal generator which may comprise: a slope control circuit configured to generate a controllable analog reference voltage according to a digital setting code value to control a slope of a ramp signal; and at least one unit current cell configured to adjust the slope of the ramp signal by adjusting a current flowing through the at least one unit current cell according to the controllable analog reference voltage generated by the slope control circuit.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyeon-June Kim, Hoe-Sam Jeong
  • Publication number: 20200366861
    Abstract: An image sensor for stably generating pulses of a precharge signal is disclosed. The image sensor includes a divider configured to generate a plurality of divided clock signals by dividing one or ore input clock signal, a precharge pulse generator configured to generate a first pulse signal by selecting any one of the plurality of divided clock signals in response to decoding signals of a first group, and generate a second pulse signal by selecting any one of the plurality of divided clock signals in response to decoding signals of a second group, and a precharge signal generator configured to generate a precharge signal by combining the first pulse signal and the second pulse signal.
    Type: Application
    Filed: October 18, 2019
    Publication date: November 19, 2020
    Inventor: Hoe Sam JEONG
  • Patent number: 10819935
    Abstract: Provided are devices having a ramp signal generator for adjusting a slope of a ramp signal by adjusting a current of a unit current circuit to adjust a step size. The ramp signal generator may include a unit current circuit including one or more current paths that allow a flow of an electrical current generated based on a ramp supply voltage, and a slope adjustment circuit configured to adjust a slope of a ramp signal by changing a current path of the electrical current flowing through the one or more current paths of the unit current circuit.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 27, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyeon-June Kim, Hoe-Sam Jeong
  • Patent number: 10694134
    Abstract: A comparison device includes a comparison circuit including input ports to receive a pixel signal and a ramp signal, respectively, and structured to compare the pixel signal and the ramp signal to output a comparison signal; a sensing circuit coupled to the comparison circuit and structured to sense a common voltage variation amount from the comparison circuit, wherein the common voltage variation amount depends on the pixel signal such that the common voltage variation amount increases as the pixel signal increases; and a tail current control circuit coupled to the sensing circuit and structured to control a tail current amount of the comparison circuit based on the common voltage variation amount.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 23, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyeon-June Kim, Hoe-Sam Jeong
  • Patent number: 10638074
    Abstract: A data readout apparatus may include a comparison circuit structured to compare a pixel signal with the ramp signal to generate a comparison result, a counter array structured to receive the comparison results to count up with each clock pulse from a first timing until a second timing to convert a counted number of clock pulses into differential data and output the differential data through differential data lines, and a sense amplifier array structured to receive the differential data to sense and amplify the differential data based on a judge clock. The sense amplifier array can include a replica delay structured to delay the judge clock and the precharge pulse signal based on a read out timing and read out the data from the counter array at the read out timing.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: April 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Min-Seok Shin, Hoe-Sam Jeong
  • Publication number: 20200111515
    Abstract: A data readout apparatus may include a comparison circuit structured to compare a pixel signal with the ramp signal to generate a comparison result, a counter array structured to receive the comparison results to count up with each clock pulse from a first timing until a second timing to convert a counted number of clock pulses into differential data and output the differential data through differential data lines, and a sense amplifier array structured to receive the differential data to sense and amplify the differential data based on a judge clock. The sense amplifier array can include a replica delay structured to delay the judge clock and the precharge pulse signal based on a read out timing and read out the data from the counter array at the read out timing.
    Type: Application
    Filed: December 31, 2018
    Publication date: April 9, 2020
    Inventors: Min-Seok Shin, Hoe-Sam Jeong
  • Publication number: 20190335126
    Abstract: Provided are devices having a ramp signal generator for adjusting a slope of a ramp signal by adjusting a current of a unit current circuit to adjust a step size. The ramp signal generator may include a unit current circuit including one or more current paths that allow a flow of an electrical current generated based on a ramp supply voltage, and a slope adjustment circuit configured to adjust a slope of a ramp signal by changing a current path of the electrical current flowing through the one or more current paths of the unit current circuit.
    Type: Application
    Filed: December 13, 2018
    Publication date: October 31, 2019
    Inventors: Hyeon-June Kim, Hoe-Sam Jeong
  • Publication number: 20190327438
    Abstract: Provided are devices having a device including a ramp signal generator which may comprise: a slope control circuit configured to generate a controllable analog reference voltage according to a digital setting code value to control a slope of a ramp signal; and at least one unit current cell configured to adjust the slope of the ramp signal by adjusting a current flowing through the at least one unit current cell according to the controllable analog reference voltage generated by the slope control circuit.
    Type: Application
    Filed: December 13, 2018
    Publication date: October 24, 2019
    Inventors: Hyeon-June Kim, Hoe-Sam Jeong
  • Patent number: 10381093
    Abstract: A nonvolatile memory device includes a nonvolatile memory cell, a sensing circuit coupled between a sensing input line coupled to a bit line of the nonvolatile memory cell and a sensing output line, a sensing output grounding portion fixing an output signal of the sensing circuit at a low level if the output signal of the sensing circuit has a low level, and a bit line grounding portion fixing a bit line voltage at a ground voltage if the output signal of the sensing circuit is fixed at a low level.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: August 13, 2019
    Assignee: SK hynix Inc.
    Inventor: Hoe Sam Jeong
  • Publication number: 20190246058
    Abstract: A comparison device includes a comparison circuit including input ports to receive a pixel signal and a ramp signal, respectively, and structured to compare the pixel signal and the ramp signal to output a comparison signal; a sensing circuit coupled to the comparison circuit and structured to sense a common voltage variation amount from the comparison circuit, wherein the common voltage variation amount depends on the pixel signal such that the common voltage variation amount increases as the pixel signal increases; and a tail current control circuit coupled to the sensing circuit and structured to control a tail current amount of the comparison circuit based on the common voltage variation amount.
    Type: Application
    Filed: December 13, 2018
    Publication date: August 8, 2019
    Inventors: Hyeon-June Kim, Hoe-Sam Jeong
  • Publication number: 20180350429
    Abstract: A precharge circuit includes a precharge block suitable for precharging a positive bit line and a negative bit line; and a precharge level adjusting block suitable for adjusting a precharge level of the precharge block using a threshold voltage value of a transistor.
    Type: Application
    Filed: May 21, 2018
    Publication date: December 6, 2018
    Inventor: Hoe-Sam JEONG
  • Patent number: 9837150
    Abstract: A nonvolatile memory device includes a nonvolatile memory cell and a variable resistive load portion. The variable resistive load portion is coupled between a bit line of the nonvolatile memory cell and a supply voltage line. The variable resistive load portion is suitable for changing a resistance value between the bit line and the supply voltage line according to a level of a supply voltage applied to the supply voltage line.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: December 5, 2017
    Assignee: SK Hynix Inc.
    Inventor: Hoe Sam Jeong
  • Publication number: 20170294232
    Abstract: A nonvolatile memory device includes a nonvolatile memory cell, a sensing circuit coupled between a sensing input line coupled to a bit line of the nonvolatile memory cell and a sensing output line, a sensing output grounding portion fixing an output signal of the sensing circuit at a low level if the output signal of the sensing circuit has a low level, and a bit line grounding portion fixing a bit line voltage at a ground voltage if the output signal of the sensing circuit is fixed at a low level.
    Type: Application
    Filed: August 10, 2016
    Publication date: October 12, 2017
    Inventor: Hoe Sam JEONG
  • Publication number: 20170243640
    Abstract: A nonvolatile memory device includes a nonvolatile memory cell and a variable resistive load portion. The variable resistive load portion is coupled between a bit line of the nonvolatile memory cell and a supply voltage line. The variable resistive load portion is suitable for changing a resistance value between the bit line and the supply voltage line according to a level of a supply voltage applied to the supply voltage line.
    Type: Application
    Filed: August 10, 2016
    Publication date: August 24, 2017
    Inventor: Hoe Sam JEONG
  • Patent number: 9704589
    Abstract: A nonvolatile memory device includes a nonvolatile memory cell coupled to a bit line. The nonvolatile memory device may include a sensing circuit configured to output a sensing output signal for sensing a status of the nonvolatile memory cell based on a sensing input signal inputted to the sensing circuit through a sensing input line. The nonvolatile memory device may include a folding circuit coupled to the bit line to output the sensing input signal having a voltage low level or a voltage high level according to a voltage level of the bit line.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: July 11, 2017
    Assignee: SK hynix Inc.
    Inventor: Hoe Sam Jeong
  • Patent number: 9627083
    Abstract: A nonvolatile memory device may include a nonvolatile memory cell and a sensing circuit. The sensing circuit is coupled to a bit line of the nonvolatile memory cell. The sensing circuit may be realized using an inverter comprised of a P-channel transistor coupled to a supply voltage line and an N-channel transistor coupled to a ground voltage. The gate of the P-channel transistor is coupled to the ground voltage.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: April 18, 2017
    Assignee: SK HYNIX INC.
    Inventor: Hoe Sam Jeong
  • Patent number: 9620185
    Abstract: A voltage supply device includes a bias generator, a control signal generator and a cell switching circuit. The bias generator divides a first supply voltage to output a plurality of divided supply voltages. The control signal generator receives the plurality of divided supply voltages to generate a plurality of control signals. The cell switching circuit receives the plurality of control signals to provide nonvolatile memory cells with one or more of a ground voltage, the first supply voltage, or a second supply voltage different from the first supply voltage. Each of the bias generator, the control signal generator and the cell switching circuit is implemented with medium voltage MOS transistors having a breakdown voltage of from approximately 7 volts to approximately 15 volts.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: April 11, 2017
    Assignee: SK Hynix Inc.
    Inventor: Hoe Sam Jeong
  • Patent number: 6657498
    Abstract: A variable gain, low noise amplifier is described, which is suitable as the input amplifier for a wireless terminal, or as the pre-amplifier stage of a wireless terminal transmitter. The amplifier may achieve variable gain by deploying a network of transistors in a parallel array, each independently selectable by a PMOS switch, and providing the variable resistance for the resonant circuit. Power dissipation can also be mitigated by using a network of driving transistors, each independently selectable by a PMOS switch. The resonant frequency of the amplifier may be made tunable by providing a selection of optional pull-up capacitors.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: December 2, 2003
    Assignee: GCT Semiconductor, Inc.
    Inventors: Joonbae Park, Hoe-Sam Jeong, Seung-Wook Lee, Won-Seok Lee, Kyeongho Lee
  • Publication number: 20020190796
    Abstract: A variable gain, low noise amplifier is described, which is suitable as the input amplifier for a wireless terminal, or as the pre-amplifier stage of a wireless terminal transmitter. The amplifier may achieve variable gain by deploying a network of transistors in a parallel array, each independently selectable by a PMOS switch, and providing the variable resistance for the resonant circuit. Power dissipation can also be mitigated by using a network of driving transistors, each independently selectable by a PMOS switch. The resonant frequency of the amplifier may be made tunable by providing a selection of optional pull-up capacitors.
    Type: Application
    Filed: July 17, 2002
    Publication date: December 19, 2002
    Applicant: GCT Semiconductor, Inc.
    Inventors: Joonbae Park, Hoe-Sam Jeong, Seung-Wook Lee, Won-Seok Lee, Kyeongho Lee
  • Patent number: 6424222
    Abstract: A variable gain, low noise amplifier is described, which is suitable as the input amplifier for a wireless terminal, or as the pre-amplifier stage of a wireless terminal transmitter. The amplifier may achieve variable gain by deploying a network of transistors in a parallel array, each independently selectable by a PMOS switch, and providing the variable resistance for the resonant circuit. Power dissipation can also be mitigated by using a network of driving transistors, each independently selectable by a PMOS switch. The resonant frequency of the amplifier may be made tunable by providing a selection of optional pull-up capacitors.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: July 23, 2002
    Assignee: GCT Semiconductor, Inc.
    Inventors: Hoe-Sam Jeong, Seung-Wook Lee, Won-Seok Lee