Abstract: According to embodiments of the present disclosure, if write operations for a memory block with efficient write operations according to a cache program mode and a memory block with a different property are mixed, the write operation is performed by switching the cache program mode to a normal program mode. Accordingly, it is possible to prevent or reduce performance degradation of the cache program mode due to a workload in which write operations of different property are mixed, thereby improving write operation efficiency.

Abstract: A storage device may determine write throughput based on a plurality of write commands received from the outside of the storage device, and write target data write-requested from the outside to a first memory area including one or more of a plurality of first type memory blocks or a second memory area including one or more of a second type memory blocks according to whether the write throughput is greater than or equal to a threshold throughput. The first type memory blocks may operate at a higher speed than the second type memory blocks.

Abstract: A storage device may load, between a first time point at which information on candidate memory regions among a plurality of memory regions is started to be sent to an external device and a second time point at which a command requesting a map segment for a target memory region among the plurality of memory regions is received from the external device, all or a part of map segments corresponding to the candidate memory regions into a buffer.

Abstract: A storage device may get a timestamp when a timestamp getting condition is satisfied, may determine a retention time of a target super memory block according to time information calibrated on the basis of the timestamp, and may determine whether to select the target super memory block as a victim memory block for a target operation, on the basis of the determined retention time.

Abstract: A data storage device may include a storage and a controller. The storage a storage including a first region of a first physical address range and a second region of a second physical address range. The controller may generate map data including a plurality of map segments, a first segment entry and a second segment entry, and store, in the second region, the map data except for a first map segment. Each of the map segments includes a set of physical addresses corresponding to a plurality of sequential logical addresses. The first segment entry includes a first segment physical address associated with the first map segment and belonging to the first physical address range, and the second segment entry includes a second segment physical address associated with a second map segment and belonging to the second physical address range.

Abstract: A memory system includes: a memory device including first memory blocks, within which a single bit is to be programmed into a memory cell by using a single level cell (SLC) method, and second memory blocks, within which two or more bits are to be programmed into a memory cell by using a multi-level cell (MLC)-or-more method, and a controller configured to program first data in the first memory blocks by using the SLC method and then migrate the first data from the first memory blocks into the second memory blocks by using the MLC-or-more method, wherein the controller is further configured to read the first or second memory blocks according to a number of free blocks included in the first memory blocks, when the read request for the second memory block is received after the specific amount of time.

Abstract: A memory system includes: a memory device; a first queue suitable for queuing commands received from a host; a second queue suitable for enqueuing the commands from the first queue and dequeuing the commands to the memory device according to the FIFO scheme; and a processor suitable for: delaying enqueuing a read command into the second queue until the program operation is successfully performed when a logical address of a write command, in response to which a program operation is being performed, is the same as a logical address corresponding to the read command enqueued in the first queue; and determining whether or not to enqueue a subsequent read command, which is enqueued in the first queue after the read command, into the second queue.

Abstract: A memory system includes: a memory device; a command queue queuing a program descriptor and a first read descriptor, and sequentially outputting the descriptors; a program manager performing an error handling operation in response to the program descriptor, the error handling operation including performing a program operation on a second physical address when a program operation performed on a first physical address fails; a fail managing buffer storing the first physical address for the failed program operation; a queue manager deleting the first read descriptor from the command queue and outputting an exception signal, when a physical address of the first read descriptor is the same as the first physical address; and a descriptor generator generating a second read descriptor including the second physical address in response to the exception signal and enqueuing the second read descriptor in the command queue, when the error handling operation passed.

Abstract: In a memory controller included in a memory system for processing a program operation fail, the memory controller controls a plurality of memory devices commonly coupled to a channel, the plurality of memory devices respectively performing preset program operations, and includes: a buffer memory for storing data to be stored in the plurality of memory devices, based on a buffer memory index; and a program error processor for acquiring fail data corresponding to a program operation fail from a fail memory device and acquiring reprogram data that is data to be stored together with the fail data, based on the buffer memory index.

Abstract: A memory system includes: a memory device including first memory blocks, within which a single bit is to be programmed into a memory cell by using a single level cell (SLC) method, and second memory blocks, within which two or more bits are to be programmed into a memory cell by using a multi-level cell (MLC)-or-more method, and a controller configured to program first data in the first memory blocks by using the SLC method and then migrate the first data from the first memory blocks into the second memory blocks by using the MLC-or-more method, wherein the controller is further configured to read the first or second memory blocks according to a number of free blocks included in the first memory blocks, when the read request for the second memory block is received after the specific amount of time.

Abstract: A memory system includes: a memory device; a host interface suitable for receiving write commands and queueing the received write commands in an interface queue; a workload manager suitable for detecting, in a cache program mode, a mixed workload when a read count is greater than a first threshold value, the read count representing a number of read commands queued in the interface queue and the mixed workload representing receipt of a mix of read and write commands; a mode manager suitable for switching from the cache program mode to a normal program mode when the mixed workload is detected; and a processor suitable for processing write commands queued in a command queue in the cache program mode and processing write commands queued in the interface queue in the normal program mode when the mixed workload is detected.

Abstract: A data storage device includes a memory cell array comprising a plurality of pages each including K memory cells of which each stores N bits therein, where N and K are positive numbers greater than or equal to 2, wherein each of the pages stores one page data constituted by N subpage data each having K bits; a cache buffer receiving and caching N subpage data of first page data from a controller; and a page buffer sequentially buffering the respective cached N subpage data of the first page data and store the respective buffered N subpage data of the first page data in the memory cell array, wherein when a write operation for Mth subpage data of the first page data is completed, the cache buffer receives and caches Mth subpage data of second page data from the controller, where M is a positive number less than N.

Abstract: A memory system includes: a memory device including a memory block, a page buffer, and first and second memory dies; a write buffer suitable for temporarily storing first and second data; a program managing unit suitable for controlling the memory device to sequentially perform first and second program operations on the memory block with the first and second data; a buffer managing unit suitable for managing the write buffer based on a scatter-gather scheme; a failure processing unit suitable for forcing the second program operation to fail, when the first program operation is a failure; and an error handling unit suitable for controlling the program managing unit to perform the first and second program operations again for the first and second data that are temporarily stored in the write buffer when the second program operation is forced to fail.

Abstract: There are provided a memory system and an operating method thereof. The memory system includes: a memory device including a plurality of semiconductor memories; and a controller for generating a plurality of command queues respectively corresponding to the plurality of semiconductor memories by queuing a plurality of commands received from a host, and controlling the plurality of semiconductor memories to perform overall operations by outputting the plurality of commands queued in the plurality of command queues, wherein the controller holds a first command queue, among the plurality of command queues, corresponding to a first semiconductor memory, among the plurality of semiconductor memories, in which a program fail has occurred.

Abstract: In a memory controller included in a memory system for processing a program operation fail, the memory controller controls a plurality of memory devices commonly coupled to a channel, the plurality of memory devices respectively performing preset program operations, and includes: a buffer memory for storing data to be stored in the plurality of memory devices, based on a buffer memory index; and a program error processor for acquiring fail data corresponding to a program operation fail from a fail memory device and acquiring reprogram data that is data to be stored together with the fail data, based on the buffer memory index.

Abstract: A data storage device includes a storage unit; and a controller configured to select a write mode by analyzing a tendency of commands received from a host device, and operate in the selected write mode to write data to the storage or to read data from the storage.

Abstract: A memory system includes: a memory device; a host interface suitable for receiving write commands and queueing the received write commands in an interface queue; a workload manager suitable for detecting, in a cache program mode, a mixed workload when a read count is greater than a first threshold value, the read count representing a number of read commands queued in the interface queue and the mixed workload representing receipt of a mix of read and write commands; a mode manager suitable for switching from the cache program mode to a normal program mode when the mixed workload is detected; and a processor suitable for processing write commands queued in a command queue in the cache program mode and processing write commands queued in the interface queue in the normal program mode when the mixed workload is detected.

Abstract: A storage device includes a memory device including a memory cell array and a page buffer group coupled to the memory cell array, and a memory controller configured to store a plurality of cache data chunks to be sequentially programmed, and configured to input a next cache data chunk corresponding to a next program sequence to the page buffer group, when programming of Least Significant Bit (LSB) data of a cache data chunk among the plurality of cache data chunks is completed.

Abstract: In a memory controller included in a memory system for processing a program operation fail, the memory controller controls a plurality of memory devices commonly coupled to a channel, the plurality of memory devices respectively performing preset program operations, and includes: a buffer memory for storing data to be stored in the plurality of memory devices, based on a buffer memory index; and a program error processor for acquiring fail data corresponding to a program operation fail from a fail memory device and acquiring reprogram data that is data to be stored together with the fail data, based on the buffer memory index.

Abstract: A memory system includes: a memory device; a first queue suitable for queuing commands received from a host; a second queue suitable for enqueuing the commands from the first queue and dequeuing the commands to the memory device according to the FIFO scheme; and a processor suitable for: delaying enqueuing a read command into the second queue until the program operation is successfully performed when a logical address of a write command, in response to which a program operation is being performed, is the same as a logical address corresponding to the read command enqueued in the first queue; and determining whether or not to enqueue a subsequent read command, which is enqueued in the first queue after the read command, into the second queue.