Abstract: A processor and a power supply ripple reduction method are provided. The processor is connected to a power supply and an external memory and includes a controller, a power control unit and a processing unit. The processing unit includes an input buffer, an arithmetic unit, and an output buffer. The controller is used to determine an initial waiting cycle number N1 and a waiting cycle decrement number N2 of the processing unit. The power supply control unit is used to transmit, when the processor starts operations, a first control signal to the processing unit according to N1 and N2. The processing unit reads, upon receiving the first control signal, data to be processed from the external memory (12), buffers the read data in the input buffer, transmits the buffered data from the input buffer to the arithmetic unit to perform computation, and saves a computation result into the output buffer.