Abstract: An output buffer circuit is provided. The output buffer circuit includes a fast slew rate (FSR) controller that detects a transition duration of an input voltage, to adjust a magnitude of a detection current generated in the detected transition duration based on information on a slew slope, and to generate a slew rate control signal as the adjustment result, and an output buffer that outputs the input voltage as a source drive signal having a slew rate or a slew slope, which is selected, in response to the slew rate control signal.

Abstract: Provided are a source driver configured to drive a display panel and a display device including the same. A source driver configured to drive a source line of a display panel includes a digital circuit configured to receive and store digital pixel data, and an analog circuit configured to convert the stored digital pixel data into an analog-signal-type gradation voltage and output the analog-signal-type gradation voltage. A static current of the analog circuit is reduced in response to a value of a timing signal corresponding to a non-driving section of the display panel.

Abstract: Provided are a method of driving a liquid crystal panel which prevents unintended digital image data from being displayed on a liquid crystal panel when power is provided or interrupted, and a source driver and a liquid crystal display apparatus. The source driver includes output buffers; output pads; and a switching unit which is disposed between the output buffers and the output pads and controls an electrical connection state of the output pads. If a level up or a level down of a power voltage occurs, the switching unit prevents output signals of the output buffers from being transmitted to the liquid crystal panel via corresponding output pads and performs at least one of a charge sharing operation for connecting the output pads to each other and a discharging operation for providing a discharge path from the output pads to a ground terminal, in a preset period.

Abstract: A power supply apparatus and a power supply method are disclosed. The power supply apparatus may include an internal power supply including a first voltage generator configured to generate a first voltage based on a pulse width modulation control signal, a charge pump configured to receive the first voltage and generate a second voltage, and an inrush current controller configured to be connected between the charge pump and the internal power supply and configured to generate the pulse width modulation control signal based on a target signal and a selection reference voltage.

Abstract: A power-off discharge circuit comprises a power voltage detection unit that detects whether a first power voltage for driving a source driver circuit is blocked and generates a discharge control signal, and a discharge unit that discharges a load circuit in a display panel based on the discharge control signal.

Abstract: A power-off discharge circuit comprises a power voltage detection unit that detects whether a first power voltage for driving a source driver circuit is blocked and generates a discharge control signal, and a discharge unit that discharges a load circuit in a display panel based on the discharge control signal.

Abstract: Provided are a delay locked loop (DLL) having a pulse width detection circuit and a method of driving the DLL. The DLL includes a pulse width detection circuit and a delay circuit. The pulse width detection circuit receives a reference clock signal, detects a pulse width of the reference clock signal, and outputs the detection result as a pulse width detection result signal. The delay circuit receives and delays the reference clock signal, and outputs the delayed reference clock signal as an output clock signal. The delay circuit receives the pulse width detection result signal from the pulse width detection circuit, and controls a time delay in the reference clock signal in response to the pulse width detection result signal.

Abstract: A power supply apparatus and a power supply method are disclosed. The power supply apparatus may include an internal power supply including a first voltage generator configured to generate a first voltage based on a pulse width modulation control signal, a charge pump configured to receive the first voltage and generate a second voltage, and an inrush current controller configured to be connected between the charge pump and the internal power supply and configured to generate the pulse width modulation control signal based on a target signal and a selection reference voltage.

Abstract: Provided are a method of driving a liquid crystal panel which prevents unintended digital image data from being displayed on a liquid crystal panel when power is provided or interrupted, and a source driver and a liquid crystal display apparatus. The source driver includes output buffers; output pads; and a switching unit which is disposed between the output buffers and the output pads and controls an electrical connection state of the output pads. If a level up or a level down of a power voltage occurs, the switching unit prevents output signals of the output buffers from being transmitted to the liquid crystal panel via corresponding output pads and performs at least one of a charge sharing operation for connecting the output pads to each other and a discharging operation for providing a discharge path from the output pads to a ground terminal, in a preset period.

Abstract: A power-off discharge circuit comprises a power voltage detection unit that detects whether a first power voltage for driving a source driver circuit is blocked and generates a discharge control signal, and a discharge unit that discharges a load circuit in a display panel based on the discharge control signal.

Abstract: Provided are a delay locked loop (DLL) having a pulse width detection circuit and a method of driving the DLL. The DLL includes a pulse width detection circuit and a delay circuit. The pulse width detection circuit receives a reference clock signal, detects a pulse width of the reference clock signal, and outputs the detection result as a pulse width detection result signal. The delay circuit receives and delays the reference clock signal, and outputs the delayed reference clock signal as an output clock signal. The delay circuit receives the pulse width detection result signal from the pulse width detection circuit, and controls a time delay in the reference clock signal in response to the pulse width detection result signal.