Patents by Inventor Hohyeuk Im
Hohyeuk Im has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10770383Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.Type: GrantFiled: May 16, 2019Date of Patent: September 8, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Hohyeuk Im
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Patent number: 10573588Abstract: A package substrate and a semiconductor package are provided. The package substrate including a substrate body having a first surface on which a semiconductor chip is mounted and a second surface opposite to the first surface, and a conductive pad at the first surface, the conductive pad elongated in a first direction, the conductive pad including a plurality of sub-bar patterns spaced apart from each other in the first direction may be provided.Type: GrantFiled: May 24, 2018Date of Patent: February 25, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: Hohyeuk Im
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Patent number: 10553529Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.Type: GrantFiled: August 31, 2016Date of Patent: February 4, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Hohyeuk Im
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Patent number: 10438879Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.Type: GrantFiled: August 31, 2016Date of Patent: October 8, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Hohyeuk Im
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Publication number: 20190273039Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.Type: ApplicationFiled: May 16, 2019Publication date: September 5, 2019Inventor: Hohyeuk Im
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Publication number: 20190080994Abstract: A package substrate and a semiconductor package are provided. The package substrate including a substrate body having a first surface on which a semiconductor chip is mounted and a second surface opposite to the first surface, and a conductive pad at the first surface, the conductive pad elongated in a first direction, the conductive pad including a plurality of sub-bar patterns spaced apart from each other in the first direction may be provided.Type: ApplicationFiled: May 24, 2018Publication date: March 14, 2019Applicant: Samsung Electronics Co., Ltd.Inventor: Hohyeuk IM
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Patent number: 9881822Abstract: A multi-stepped boat assembly includes a stack boat having at least one stack hole configured to receive a first semiconductor package and a second semiconductor package vertically stacked on the first semiconductor package in the stack hole. A guide boat has at least one guide hole vertically aligned with the at least one stack hole. The guide boat is removably attachable to the stack boat. An inner sidewall of the stack hole includes a first step configured to receive the first semiconductor package, and a second step provided on the first step and configured to receive the second semiconductor package. The guide hole extends toward the stack hole to guide movement of the first semiconductor package to the first step.Type: GrantFiled: September 16, 2015Date of Patent: January 30, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sunrak Kim, Hohyeuk Im
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Publication number: 20170117215Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.Type: ApplicationFiled: August 31, 2016Publication date: April 27, 2017Inventor: HOHYEUK IM
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Publication number: 20160111347Abstract: Provided are a semiconductor package and a method of fabricating the same. The package substrate includes a hole, which may be used to form a mold layer without any void. The mold layer may be partially removed to expose a lower conductive pattern. Accordingly, it is possible to improve routability of solder balls.Type: ApplicationFiled: December 30, 2015Publication date: April 21, 2016Inventors: Jongkook Kim, Su-min Park, Soojeoung Park, Bona Baek, Hohyeuk Im, Byoungwook Jang, Yoonha Jung
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Publication number: 20160086834Abstract: A multi-stepped boat assembly includes a stack boat having at least one stack hole configured to receive a first semiconductor package and a second semiconductor package vertically stacked on the first semiconductor package in the stack hole. A guide boat has at least one guide hole vertically aligned with the at least one stack hole. The guide boat is removably attachable to the stack boat. An inner sidewall of the stack hole includes a first step configured to receive the first semiconductor package, and a second step provided on the first step and configured to receive the second semiconductor package. The guide hole extends toward the stack hole to guide movement of the first semiconductor package to the first step.Type: ApplicationFiled: September 16, 2015Publication date: March 24, 2016Inventors: Sunrak Kim, Hohyeuk Im
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Patent number: 9252031Abstract: Provided is a semiconductor package including a lower package, an interposer on the lower package, and an upper package on the interposer. The lower package may include a lower package substrate, a lower semiconductor chip on the lower package substrate, and a lower heat-transfer layer on the lower semiconductor chip. The interposer may include an interposer substrate, first and second heat-transfer openings defined by recessed bottom and top surfaces, respectively, of the interposer substrate, an upper interposer heat-transfer pad disposed in the second heat-transfer opening, and an upper heat-transfer layer disposed on the upper interposer heat-transfer pad. The upper package may include an upper package substrate, an upper package heat-transfer pad, which may be disposed in a third heat-transfer opening defined by a recessed bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the upper package substrate.Type: GrantFiled: September 23, 2014Date of Patent: February 2, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hohyeuk Im, Jongkook Kim, Gowoon Seong, SeokWon Lee, Byoungwook Jang, Eunseok Cho
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Patent number: 9252095Abstract: Provided are a semiconductor package and a method of fabricating the same. The package substrate includes a hole, which may be used to form a mold layer without any void. The mold layer may be partially removed to expose a lower conductive pattern. Accordingly, it is possible to improve routability of solder balls.Type: GrantFiled: June 20, 2013Date of Patent: February 2, 2016Assignee: Samsung Electronics Co., LTD.Inventors: Jongkook Kim, Su-min Park, Soojeoung Park, Bona Baek, Hohyeuk Im, Byoungwook Jang, Yoonha Jung
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Publication number: 20150084170Abstract: Provided is a semiconductor package including a lower package, an interposer on the lower package, and an upper package on the interposer. The lower package may include a lower package substrate, a lower semiconductor chip on the lower package substrate, and a lower heat-transfer layer on the lower semiconductor chip. The interposer may include an interposer substrate, first and second heat-transfer openings defined by recessed bottom and top surfaces, respectively, of the interposer substrate, an upper interposer heat-transfer pad disposed in the second heat-transfer opening, and an upper heat-transfer layer disposed on the upper interposer heat-transfer pad. The upper package may include an upper package substrate, an upper package heat-transfer pad, which may be disposed in a third heat-transfer opening defined by a recessed bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the upper package substrate.Type: ApplicationFiled: September 23, 2014Publication date: March 26, 2015Inventors: Hohyeuk IM, JONGKOOK KIM, Gowoon SEONG, SeokWon LEE, BYOUNGWOOK JANG, EUNSEOK CHO
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Publication number: 20140008795Abstract: Provided are a semiconductor package and a method of fabricating the same. The package substrate includes a hole, which may be used to form a mold layer without any void. The mold layer may be partially removed to expose a lower conductive pattern. Accordingly, it is possible to improve routability of solder balls.Type: ApplicationFiled: June 20, 2013Publication date: January 9, 2014Inventors: Jongkook KIM, Su-min PARK, Soojeoung PARK, Bona BAEK, Hohyeuk IM, Byoungwook JANG, Yoonha JUNG
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Patent number: 8623743Abstract: Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.Type: GrantFiled: January 15, 2013Date of Patent: January 7, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Do Lee, JongKook Kim, SeokWon Lee, Jaesik Lee, Hohyeuk Im, Su-Min Park
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Patent number: 8354735Abstract: Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.Type: GrantFiled: September 3, 2010Date of Patent: January 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Do Lee, Jongkook Kim, Seok Won Lee, Jaesik Lee, Hohyeuk Im, Su-min Park
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Publication number: 20110057297Abstract: Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.Type: ApplicationFiled: September 3, 2010Publication date: March 10, 2011Inventors: Jung-Do Lee, Jongkook Kim, Seok Won Lee, Jaesik Lee, Hohyeuk Im, Su-min Park