Abstract: A circuit configured to detect a threshold voltage includes a first delay circuit, a second delay circuit and a controller. The first delay circuit has a first sensitivity to threshold voltage of a transistor. The first delay circuit may be configured to generate a first output signal delayed with respect to the input signal by a first delay time that changes depending on the digital control code. The second delay circuit has a second sensitivity that is higher than the first sensitivity. The second delay circuit may be configured to generate a second output signal delayed with respect to the input signal by a second delay time. The controller may compare the first and second output signals and may generate a digital output code corresponding to the digital control code when the first delay time is equal to the second delay time to indicate the threshold voltage of the transistor.

Abstract: A memory device includes core dies including memory cell arrays, and a buffer die electrically connected to the core dies through one or more through silicon vias. The buffer die includes a DQS generation circuit that receives an external clock signal from an external device and generates data strobe signals based on the external clock signal for communicating data with the core dies, a DQS calibration circuit that detects a latency of each of plural rank signal that are received from the core dies based on the data strobe signals, respectively, and a coefficient decision circuit that detects a threshold voltage code of the buffer die, applies a weight to the latency of each rank signal based on the threshold voltage code to generate a weighted calibration code for each rank signal, and transmits the weighted calibration codes to respective ones of the core dies.

Abstract: An apparatus for correcting an error of a clock signal may include a phase adjuster that corrects an error of half-rate clock signals based on an error correction signal to output an error-corrected clock signal, a phase splitter that outputs quadrature clock signals from the error-corrected clock signal, an error detector that outputs an internal clock signal based on one of the quadrature clock signals, selects two quadrature clock signals among the quadrature clock signals based on a clock selection signal, and detects errors of the two quadrature clock signals based on an error check signal to output a correction request signal, and a controller that outputs a mode selection signal and the clock selection signal based on the internal clock signal and that outputs the error correction signal and the error check signal based on the mode selection signal, the clock selection signal, and the correction request signal.

Abstract: An apparatus for correcting an error of a clock signal may include a phase adjuster that corrects an error of half-rate clock signals based on an error correction signal to output an error-corrected clock signal, a phase splitter that outputs quadrature clock signals from the error-corrected clock signal, an error detector that outputs an internal clock signal based on one of the quadrature clock signals, selects two quadrature clock signals among the quadrature clock signals based on a clock selection signal, and detects errors of the two quadrature clock signals based on an error check signal to output a correction request signal, and a controller that outputs a mode selection signal and the clock selection signal based on the internal clock signal and that outputs the error correction signal and the error check signal based on the mode selection signal, the clock selection signal, and the correction request signal.