Patents by Inventor HOI HIN LOO

HOI HIN LOO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10018668
    Abstract: A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 10, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hoi Hin Loo, Soh Ying Seah
  • Publication number: 20180011138
    Abstract: A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die.
    Type: Application
    Filed: September 22, 2017
    Publication date: January 11, 2018
    Inventors: HOI HIN LOO, SOH YING SEAH
  • Patent number: 9772372
    Abstract: A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: September 26, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hoi Hin Loo, Soh Ying Seah
  • Publication number: 20150212143
    Abstract: A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die.
    Type: Application
    Filed: January 30, 2014
    Publication date: July 30, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: HOI HIN LOO, SOH YING SEAH