Abstract: In a pattern formation method for a semiconductor device fabrication, an original pattern for manufacturing a photomask is acquired, a modified original pattern is obtained by performing an optical proximity correction on the original pattern, a sub-resolution assist feature (SRAF) seed map with respect to the modified original pattern indicating locations where an image quality is improved by an SRAF pattern is obtained, SRAF patterns are placed around the original pattern, the SRAF patterns and the modified original pattern are output as mask data, and the photo mask is manufactured using the mask data.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a first conductive feature embedded in a top portion of the substrate, a dielectric layer over the substrate, and a second conductive feature surrounded by the dielectric layer and in contact with the first conductive feature. The first conductive feature includes a metal layer and a reflective layer on the metal layer. The reflective layer has a reflectivity higher than the metal layer.

Abstract: The present disclosure provides a method for forming interconnect structures. The method includes providing a semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer over the substrate, wherein the resist layer has an exposure threshold; providing a radiation with an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer while a sum of the incident exposure dose and a reflected exposure dose from a top surface of the conductive feature is larger than the exposure threshold of the resist layer, thereby forming a latent pattern above the conductive feature; and developing the resist layer to form a patterned resist layer.

Abstract: The present disclosure provides a method for forming interconnect structures. The method includes providing a semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer over the substrate, wherein the resist layer has an exposure threshold; providing a radiation with an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer while a sum of the incident exposure dose and a reflected exposure dose from a top surface of the conductive feature is larger than the exposure threshold of the resist layer, thereby forming a latent pattern above the conductive feature; and developing the resist layer to form a patterned resist layer.

Abstract: A method for patterning fins for FinFET devices are disclosed. The method includes forming elongated protrusions on a semiconductor substrate and forming a mask covering a first portion of the elongated protrusions. The method further includes forming a spacer surrounding the mask. The mask and the spacer together cover a second portion of the elongated protrusions. The method further includes removing a portion of the elongated protrusions not covered by the mask and the spacer. In an embodiment, an outer boundary of the spacer and the mask corresponds to an outer boundary of a non-rectangular pattern.

Abstract: Provided herein is a method of improving a transference of a mask pattern into a material layer on a semiconductor wafer. The method includes steps of receiving a semiconductor mask made from a desired design layout and of patterning the material layer present on a plurality of semiconductor wafers with the mask having the mask pattern and an illumination pattern. The method further includes steps of identifying defects and/or defect patterns in the transference of the mask pattern on the plurality of semiconductor wafers, determining an illumination modification, and applying the illumination modification to the illumination pattern to create a modified illumination pattern. Additional methods and associated systems are also provided.

Abstract: A method for making a mask includes receiving an integrated circuit (IC) design layout and identifying at least one targeted-feature-surrounding-location (TFSL) in the IC design layout, wherein TFSL is identified by a model-based approach. The method further includes inserting at least one phase bar (PB) in the IC design layout and performing an optical proximity correction (OPC) to the IC design layout having the at least one PB to form a modified IC design layout. A mask is then fabricated based on the modified IC design layout.

Abstract: A method for patterning fins for FinFET devices are disclosed. The method includes forming elongated protrusions on a semiconductor substrate and forming a mask covering a first portion of the elongated protrusions. The method further includes forming a spacer surrounding the mask. The mask and the spacer together cover a second portion of the elongated protrusions. The method further includes removing a portion of the elongated protrusions not covered by the mask and the spacer. In an embodiment, an outer boundary of the spacer and the mask corresponds to an outer boundary of a non-rectangular pattern.

Abstract: Methods for patterning fins for fin-like field-effect transistor (FinFET) devices are disclosed. An exemplary method includes providing a semiconductor substrate, forming a plurality of elongated protrusions on the semiconductor substrate, the elongated protrusions extending in a first direction, and forming a mask covering a first portion of the elongated protrusions, the mask being formed of a first material having a first etch rate. The method also includes forming a spacer surrounding the mask, the spacer being formed of a second material with an etch rate lower than the etch rate of the first material, the mask and the spacer together covering a second portion of the elongated protrusions larger than the first portion of the elongated protrusions. Further, the method includes removing a remaining portion of the plurality of elongated protrusions not covered by the mask and spacer.

Abstract: Provided herein is a method of improving a transference of a mask pattern into a material layer on a semiconductor wafer. The method includes steps of receiving a semiconductor mask made from a desired design layout and of patterning the material layer present on a plurality of semiconductor wafers with the mask having the mask pattern and an illumination pattern. The method further includes steps of identifying defects and/or defect patterns in the transference of the mask pattern on the plurality of semiconductor wafers, determining an illumination modification, and applying the illumination modification to the illumination pattern to create a modified illumination pattern. Additional methods and associated systems are also provided.

Abstract: Methods for patterning fins for fin-like field-effect transistor (FinFET) devices are disclosed. An exemplary method includes providing a semiconductor substrate, forming a plurality of elongated protrusions on the semiconductor substrate, the elongated protrusions extending in a first direction, and forming a mask covering a first portion of the elongated protrusions, the mask being formed of a first material having a first etch rate. The method also includes forming a spacer surrounding the mask, the spacer being formed of a second material with an etch rate lower than the etch rate of the first material, the mask and the spacer together covering a second portion of the elongated protrusions larger than the first portion of the elongated protrusions. Further, the method includes removing a remaining portion of the plurality of elongated protrusions not covered by the mask and spacer.

Abstract: A method for making a mask includes receiving an integrated circuit (IC) design layout and identifying at least one targeted-feature-surrounding-location (TFSL) in the IC design layout, wherein TFSL is identified by a model-based approach. The method further includes inserting at least one phase bar (PB) in the IC design layout and performing an optical proximity correction (OPC) to the IC design layout having the at least one PB to form a modified IC design layout. A mask is then fabricated based on the modified IC design layout.

Abstract: A method for making a mask for an integrated circuit (IC) design includes receiving an IC design layout having a plurality IC features and performing a targeted-feature-surrounding (TFS) checking operation to identify a targeted-feature-surrounding-location (TFSL) in the IC design layout. The method also includes inserting a phase-bar (PB) to the TFSL, performing an optical proximity correction (OPC) to the IC design layout having the PB to form a modified IC design layout and providing the modified IC design layout for fabrication of the mask.

Abstract: A method for making a mask for an integrated circuit (IC) design includes receiving an IC design layout having a plurality IC features and performing a targeted-feature-surrounding (TFS) checking operation to identify a targeted-feature-surrounding-location (TFSL) in the IC design layout. The method also includes inserting a phase-bar (PB) to the TFSL, performing an optical proximity correction (OPC) to the IC design layout having the PB to form a modified IC design layout and providing the modified IC design layout for fabrication of the mask.

Abstract: The present disclosure provides a photomask. The photomask includes a substrate. The photomask also includes a plurality of patterns disposed on the substrate. Each pattern is phase shifted from adjacent patterns by different amounts in different directions. The present disclosure also includes a method for performing a lithography process. The method includes forming a patternable layer over a wafer. The method also includes performing an exposure process to the patternable layer. The exposure process is performed at least in part through a phase shifted photomask. The phase shifted photomask contains a plurality of patterns that are each phase shifted from adjacent patterns by different amounts in different directions. The method includes patterning the patternable layer.

Abstract: A method which directly incorporates patterning fidelity into the design of a patterning system is provided. A production result of a target pattern is simulated according to a set of design parameters to obtain a simulated pattern. The target pattern is compared with the simulated pattern to obtain a patterning fidelity, and the values of the set of design parameters of the patterning system are adjusted according to a target patterning fidelity to optimize the values of the set of design parameters of the patterning system.

Abstract: A method which directly incorporates patterning fidelity into the design of a patterning system is provided. A production result of a target pattern is simulated according to a set of design parameters to obtain a simulated pattern. The target pattern is compared with the simulated pattern to obtain a patterning fidelity, and the values of the set of design parameters of the patterning system are adjusted according to a target patterning fidelity to optimize the values of the set of design parameters of the patterning system.