Abstract: First electronic device includes a communication interface and a processor. The processor is configured to: receive, from the second electronic device, an incoming message destined for the first electronic device, transmit, to the third electronic device, message information related to the incoming message, the message information being used for displaying the incoming message on the third electronic device, transmit preset texts to the third electronic device, the preset texts being stored in the first electronic device to be used for replying to messages receivable by the first electronic device, based on one of the preset texts being selected by a user input among the preset texts displayed on the third electronic device, receive response information from the third electronic device, the response information being related to the one of the preset texts, and transmit, to the second electronic device, a response message including the one of the preset texts.

Abstract: An X-ray source is disposed and a detector is disposed adjacent to the X-ray source. A test specimen holder is disposed between the X-ray source and the detector. A filter is disposed between the X-ray source and the test specimen holder. The filter has a plate-shaped semiconductor, a granular semiconductor, or a combination thereof.

Abstract: An X-ray source is disposed and a detector is disposed adjacent to the X-ray source. A test specimen holder is disposed between the X-ray source and the detector. A filter is disposed between the X-ray source and the test specimen holder. The filter has a plate-shaped semiconductor, a granular semiconductor, or a combination thereof.

Abstract: An X-ray source is disposed and a detector is disposed adjacent to the X-ray source. A test specimen holder is disposed between the X-ray source and the detector. A filter is disposed between the X-ray source and the test specimen holder. The filter has a plate-shaped semiconductor, a granular semiconductor, or a combination thereof.

Abstract: An X-ray source is disposed and a detector is disposed adjacent to the X-ray source. A test specimen holder is disposed between the X-ray source and the detector. A filter is disposed between the X-ray source and the test specimen holder. The filter has a plate-shaped semiconductor, a granular semiconductor, or a combination thereof.

Abstract: An X-ray source is disposed and a detector is disposed adjacent to the X-ray source. A test specimen holder is disposed between the X-ray source and the detector. A filter is disposed between the X-ray source and the test specimen holder. The filter has a plate-shaped semiconductor, a granular semiconductor, or a combination thereof.

Abstract: Provided is a method for testing adhesion. The method includes forming thin films on a substrate; attaching an elastic plate to the substrate, wherein the elastic plate has a larger elastic coefficient than the substrate; and performing an adhesion test on the thin films using an adhesion test apparatus.

Abstract: Provided is a method for testing adhesion. The method includes forming thin films on a substrate; attaching an elastic plate to the substrate, wherein the elastic plate has a larger elastic coefficient than the substrate; and performing an adhesion test on the thin films using an adhesion test apparatus.

Abstract: A precondition reliability test of a semiconductor package, to determine a propensity of the package to delaminate, includes a baking test of drying the package, a moisture soaking test of moisturizing the dried package, a reflow test of heat-treating the moisturized package using hot air convection, and a three-dimensional imaging of the package to acquire a 3-D image of a surface of the package. The three-dimensional imaging is preferably carried out using a Moire interferometry technique during the course of the reflow test. Therefore, the delamination of the package can be observed in real time so that data on the start and rapid development of the delamination can be produced. The method also allows data which can be ordered as a Weibull Plot to be produced, thereby enabling a quantitative analysis of the reliability test results.

Abstract: A circuit board having heating elements and a hermetically sealed multi-chip package. The multi-chip package includes a plurality of semiconductor chips, a substrate electrically coupled to the plurality of semiconductor chips, heat dissipation means, and a plurality of thermal interfaces disposed between the semiconductor chips and the heat dissipation means. The heat dissipation means forms a hermetically sealed cavity that encloses the semiconductor chips and at least a portion of the substrate. The circuit board includes a chip mounting surface, a chip mounting area on the chip mounting surface, the chip mounting area including a plurality of lands, and heating elements connected to the lands, the heating elements capable heating a joint formed between the lands and electrode pads of a semiconductor chip.

Abstract: Example embodiments of a semiconductor package are provided. In accordance with an example embodiment, a semiconductor package may include an external terminal connected to a concave surface of a bottom pad, wherein the bottom pad is recessed into a substrate. In accordance with another example embodiment, a semiconductor package may include at least one external terminal, a flexible substrate having a first surface with a plurality of convex portions and a second surface opposite the first surface having a plurality of concave portions, wherein the at least one terminal is recessed into the substrate and at least one of the concave portions surrounds a portion of the at least one external terminal.

Abstract: A semiconductor package and a method for forming the same are provided. The semiconductor package comprises a chip having an active surface and a back surface. The semiconductor package further comprises a substrate having an upper surface and a lower surface opposite the upper surface. The chip is electrically connected to the upper surface of the substrate. A lid is thermally coupled to the back surface of the chip. A thermal interface material (TIM) is located between the chip and the lid. The TIM includes voids to reduce thermomechanical stresses applied on the chip and the TIM, thereby preventing package cracks.

Abstract: In the method, a conductive pad of the board is etched to a depth that is greater than 50% and less than 100% of a thickness of the conductive pad. Subsequently, a solder ball may be formed on the etched conductive pad. For example, the conductive pad may be copper.

Abstract: An array of solder structures comprising a plurality of radially-curved exterior surfaces, each one enclosing a predetermined-sized cavity that can be used for flexibly joining together at predetermined conductive contact points two planar elements having dissimilar properties. By assembling the two planar elements in a tiered arrangement, one planar element having an array of annular conductive pads and the other planar element having either a corresponding array of annular or circular conductive pads, separated by an array of spherical solder balls comprised of solder and a fluxing agent, a hollow solder structure can be created during a melting and subsequent cooling of the solder compound. The plasticity/resiliency characteristics of the resulting hollow solder structure absorbs lateral movement of the two planar elements relative to each other without degradation of the solder joint.

Abstract: A semiconductor package and a method for forming the same are provided. The semiconductor package comprises a chip having an active surface and a back surface. The semiconductor package further comprises a substrate having an upper surface and a lower surface opposite the upper surface. The chip is electrically connected to the upper surface of the substrate. A lid is thermally coupled to the back surface of the chip. A thermal interface material (TIM) is located between the chip and the lid. The TIM includes voids to reduce thermomechanical stresses applied on the chip and the TIM, thereby preventing package cracks.

Abstract: According to embodiments of the invention, a multi-chip package includes a soft element which is more elastic and flexible than the encapsulant on the sides or upper surface of the chips. Therefore, stress concentration and chip crack is prevented by ensuring vertical mobility of the chips.

Abstract: A semiconductor package and a method for forming the same are provided. The semiconductor package comprises a chip having an active surface and a back surface. The semiconductor package further comprises a substrate having an upper surface and a lower surface opposite the upper surface. The chip is electrically connected to the upper surface of the substrate. A lid is thermally coupled to the back surface of the chip. A thermal interface material (TIM) is located between the chip and the lid. The TIM includes voids to reduce thermomechanical stresses applied on the chip and the TIM, thereby preventing package cracks.

Abstract: A solder structure comprising a radially-curved exterior surface enclosing a predetermined-sized cavity used for flexibly joining together at predetermined conductive contact points two planar elements having dissimilar properties. By assembling the two planar elements in a tiered arrangement, one planar element having an annular conductive pad and the other planar element having either a corresponding annular or circular conductive pad, separated by a spherical solder compound comprised of solder and a fluxing agent, a hollow solder structure can be created during a melting and subsequent cooling of the solder compound. The plasticity/resiliency characteristics of the resulting hollow solder structure absorbs lateral movement of the two planar elements relative to each other without degradation of the solder joint.

Abstract: A semiconductor package and a method for forming the same are provided. The semiconductor package comprises a chip having an active surface and a back surface. The semiconductor package further comprises a substrate having an upper surface and a lower surface opposite the upper surface. The chip is electrically connected to the upper surface of the substrate. A lid is thermally coupled to the back surface of the chip. A thermal interface material (TIM) is located between the chip and the lid. The TIM includes voids to reduce thermomechanical stresses applied on the chip and the TIM, thereby preventing package cracks.

Abstract: An array of solder structures comprising a plurality of radially-curved exterior surfaces, each one enclosing a predetermined-sized cavity that can be used for flexibly joining together at predetermined conductive contact points two planar elements having dissimilar properties. By assembling the two planar elements in a tiered arrangement, one planar element having an array of annular conductive pads and the other planar element having either a corresponding array of annular or circular conductive pads, separated by an array of spherical solder balls comprised of solder and a fluxing agent, a hollow solder structure can be created during a melting and subsequent cooling of the solder compound. The plasticity/resiliency characteristics of the resulting hollow solder structure absorbs lateral movement of the two planar elements relative to each other without degradation of the solder joint.