Abstract: The present invention relates to a transformed human hepatic stellate cell line, and a use thereof. The hepatic stellate cell line according to the present invention exhibits an improvement in drug response, and when co-cultured with hepatic stellate cells, does not exhibit a functional decrease in the hepatic cells, and thus can be advantageously used in an in vitro culture model.

Abstract: Manufactured capillary tubes can include: a tubular member; and a coating applied partially covering the tubular member, the coating defining a window where the tubular member is free of the coating. Kits containing and methods related to the capillary tubes can be used for the cryopreservation of cells.

Abstract: A method of detecting stress of an integrated circuit including first and second patterns formed from different materials may comprise: determining one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions; calculating areas of the second pattern at the divided regions; and/or detecting a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.

Abstract: Manufactured capillary tubes can include: a tubular member; and a coating applied partially covering the tubular member, the coating defining a window where the tubular member is free of the coating. Kits containing and methods related to the capillary tubes can be used for the cryopreservation of cells.

Abstract: Provided are a semiconductor device, a semiconductor package, and an electronic system. The device includes a substrate having a front side and a back side disposed opposite the front side. An internal circuit is disposed on or near to the front side of the substrate. Signal I/O through-via structures are disposed in the substrate. Back side conductive patterns are disposed on the back side of the substrate and electrically connected to the signal I/O through-via structures. A back side conductive structure is disposed on the back side of the substrate and spaced apart from the signal I/O through-via structures. The back side conductive structure includes parallel supporter portions.

Abstract: A method of detecting stress of an integrated circuit including first and second patterns formed from different materials may comprise: determining one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions; calculating areas of the second pattern at the divided regions; and/or detecting a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.

Abstract: Provided are a semiconductor device, a semiconductor package, and an electronic system. The device includes a substrate having a front side and a back side disposed opposite the front side. An internal circuit is disposed on or near to the front side of the substrate. Signal I/O through-via structures are disposed in the substrate. Back side conductive patterns are disposed on the back side of the substrate and electrically connected to the signal I/O through-via structures. A back side conductive structure is disposed on the back side of the substrate and spaced apart from the signal I/O through-via structures. The back side conductive structure includes parallel supporter portions.

Abstract: Manufactured capillary tubes can include: a tubular member; and a coating applied partially covering the tubular member, the coating defining a window where the tubular member is free of the coating. Kits containing and methods related to the capillary tubes can be used for the cryopreservation of cells.

Abstract: Disclosed herein is a Wireless Broadband (WiBro) Universal Serial Bus (USB) modem device having a storage device and a WiBro communication device. A USB hub is connected to the USB interface of the WiBro communication device and the USB interface of the storage device, and configured to relay data to a user terminal through a USB connector. A switching mode power supply unit is configured to have a DC-DC switching mode, receive power from the user terminal, and apply the power by performing high-speed switching so that the WiBro communication device and the storage device are simultaneously driven. The switching mode power supply unit includes a dual output switching mode power supply unit and a single output switching mode power supply unit.

Abstract: A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line.

Abstract: A signal processing system of a multiplexed FBG sensor using CDMA includes a pseudo random bit sequences (PRBS) generator for generating pseudo random bit sequence; a LED for light-emitting at a pseudo random bit from the PRBS generator; a fiber coupler for transmitting a light signal from the LED into a FBG sensor portion and passing signals reflected by the FBG sensor portion herethrough; the FBG sensor portion for receiving/reflecting the light signal via an optic fiber to forward it back to the fiber coupler; an FBG filter portion for filtering the signal reflected by the FBG sensor portion and passed through the fiber coupler; photo detector for converting the light signal from the FBG filter portion into the electrical signal; a delaying portion for delaying a pseudo random bit signal from the PRBS generator for a predetermined time period; a mixing portion for mixing the delay signal from the delaying portion and the output signal from the photo detector; and at least one auto-correlation device for in

Abstract: A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line.

Abstract: A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line.

Abstract: A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line.

Abstract: A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line.

Abstract: A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line.

Abstract: A signal processing system of a multiplexed FBG sensor using CDMA comprises a pseudo random bit sequences (PRBS) generator for generating pseudo random bit sequence; a LED for light-emitting at a pseudo random bit from the PRBS generator; a fiber coupler fro transmitting a light signal from the LED into a FBG sensor portion and passing signals reflected by the FBG sensor portion therethrough; the FBG sensor portion for receiving/reflecting the light signal via an optic fiber to forward it back to the fiber coupler; an FBG filter portion for filtering the signal reflected by the FBG sensor portion and passed through the fiber coupler; a photo detector for converting the light signal from the FBG filter portion into the electrical signal; a delaying portion for delaying a pseudo random bit signal from the PRBS generator for a predetermined time period; a mixing portion for mixing the delay signal from the delaying portion and the output signal from the photo detector; and at least one auto-correlation device fo