Abstract: Provided is a refrigerator including a main body including a storeroom, a door body arranged to open or close the storeroom, a decoration panel coupled to a front side of the door body, and a holder mounted on the front side of the door body to be coupled to the decoration panel. The door body includes a rear case defining a rear side of the door body, and a main case defining front and sides of the door body. The main case includes a front part defining the front side of the door body and having an installation groove in which to install the holder, side parts defining sides of the door body, and a rear coupler coupled to the rear case. The main case is formed by bending a single metal board.

Abstract: A golf training apparatus is disclosed. The disclosed golf training apparatus comprises of a pair of golf alignment sticks equipped with a coupling mechanism based on loosely fitting sleeves that can freely slide along the length of the sticks and freely rotate around the axis of the sticks. A second coupling mechanism is included that is similar to the first but is positioned in a fixed location and made to be non-sliding in its position. The combined features produce a golf training aid that is highly functional, user-friendly and convenient to use, thereby encouraging frequent use of the product.

Abstract: A nonvolatile memory device may include a variable sampler configured to process a data signal in an amplifier mode or a sampler mode in response to a control signal, a selection circuit configured to transmit the data signal output from the variable sampler to a flip-flop via a delay unit or to the flip-flop via a path that bypasses the delay unit in response to the control signal, a converter configured to amplify a data strobe signal, a clock distribution network configured to transmit the data strobe signal amplified by the converter to the variable sampler or delay the amplified data strobe signal for a predetermined time and transmit the amplified data strobe signal to the flip-flop in response to the control signal, and a path controller configured to generate the control signal according to an input/output mode.

Abstract: An input/output circuit of a nonvolatile memory device and a nonvolatile memory device. The input/output circuit of a nonvolatile memory device includes a driver, which is configured to output data from the nonvolatile memory device to a data line, and a power gating circuit, which is connected between the driver and a power terminal or between the driver and a ground terminal and configured to block a leakage current of the driver. The power gating circuit includes a plurality of transistors electrically connected in parallel and having threshold voltages of different magnitudes, respectively.

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

Abstract: Methods and apparatuses for creating solar cell assemblies with bonded interlayers are disclosed. In summary, the present invention describes an apparatus and method for making a solar cell assembly with transparent conductive bonding interlayers. An apparatus in accordance with the present invention comprises a substrate, a first solar cell, coupled to a first side of the substrate, wherein the first solar cell comprises a first Transparent Conductive Coating (TCC) layer coupled to a first polarity electrode of the first solar cell, and a second solar cell, the second solar cell being bonded to the first solar cell by bonding the first TCC layer to the second solar cell.

Abstract: A multifunctional composite panel and a system for fabricating the multifunctional composite panel are disclosed. The multifunctional composite panel may include a plurality of structural layers and a plurality of photovoltaic layers disposed adjacent the plurality of structural layers. The structural layers may include a plurality of alternating layers where each of the alternating layers includes a first layer and a second layer. The first layer may include one or more polymers and the second layer may include one or more inorganic materials. The system for fabricating the multifunctional composite panel may include a based configured to support the multifunctional composite panel and a plurality of application heads disposed proximal the based and configured to form layers of the multifunctional composite panel.

Abstract: A method for fabricating a multifunctional composite panel is disclosed. The method can include forming a plurality of structural layers, and forming a plurality of photovoltaic layers adjacent the plurality of structural layers. Forming the plurality of structural layers can include forming alternating layers of a conductive organic material and an inorganic material. Forming the alternating layers can include forming a first layer from the conductive organic material, and forming a second layer adjacent the first layer from the inorganic material. The multifunctional composite panel can have a thickness of from about 1 mm to about 30 mm.

Abstract: A method for fabricating a multifunctional composite panel is disclosed. The method can include forming a plurality of structural layers, and forming a plurality of photovoltaic layers adjacent the plurality of structural layers. Forming the plurality of structural layers can include forming alternating layers of a conductive organic material and an inorganic material. Forming the alternating layers can include forming a first layer from the conductive organic material, and forming a second layer adjacent the first layer from the inorganic material. The multifunctional composite panel can have a thickness of from about 1 mm to about 30 mm.

Abstract: A hyperspectral camera apparatus is disclosed. The disclosed hyperspectral camera includes a plurality of semiconductor light sources to illuminate the subject with different wavelengths of light, an image sensor to acquire the image of the subject illuminated by the semiconductor light sources, and at least one optical filter provided in front of the image sensor to selectively transmit particular wavelengths of light onto the sensor.

Abstract: A hyperspectral camera apparatus is disclosed. The disclosed hyperspectral camera includes a plurality of semiconductor light sources to illuminate the subject with different wavelengths of light, an image sensor to acquire the image of the subject illuminated by the semiconductor light sources, and at least one optical filter provided in front of the image sensor to selectively transmit particular wavelengths of light onto the sensor.

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor active region, a semiconductor contact layer, at least one metal migration semiconductor barrier layer, and a metal contact. The metal migration semiconductor barrier layer may be embedded within the semiconductor contact layer. Furthermore, the metal migration semiconductor barrier layer may be located underneath or above and in intimate contact with the semiconductor contact layer. The metal migration semiconductor barrier layer and the semiconductor contact layer form a contact structure that prevents metals from migrating from the metal contact into the semiconductor active layer during long-term exposure to high temperatures.

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor active region, a semiconductor contact layer, at least one metal migration semiconductor barrier layer, and a metal contact. The metal migration semiconductor barrier layer may be embedded within the semiconductor contact layer. Furthermore, the metal migration semiconductor barrier layer may be located underneath or above and in intimate contact with the semiconductor contact layer. The metal migration semiconductor barrier layer and the semiconductor contact layer form a contact structure that prevents metals from migrating from the metal contact into the semiconductor active layer during long-term exposure to high temperatures.

Abstract: Methods and apparatuses for creating solar cell assemblies with bonded interlayers are disclosed. In summary, the present invention describes an apparatus and method for making a solar cell assembly with transparent conductive bonding interlayers. An apparatus in accordance with the present invention comprises a substrate, a first solar cell, coupled to a first side of the substrate, wherein the first solar cell comprises a first Transparent Conductive Coating (TCC) layer coupled to a first polarity electrode of the first solar cell, and a second solar cell, the second solar cell being bonded to the first solar cell by bonding the first TCC layer to the second solar cell.

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor active region, a semiconductor contact layer, at least one metal migration semiconductor barrier layer, and a metal contact. The metal migration semiconductor barrier layer may be embedded within the semiconductor contact layer. Furthermore, the metal migration semiconductor barrier layer may be located underneath or above and in intimate contact with the semiconductor contact layer. The metal migration semiconductor barrier layer and the semiconductor contact layer form a contact structure that prevents metals from migrating from the metal contact into the semiconductor active layer during long-term exposure to high temperatures.