Abstract: A system for providing on-chip voltage supply includes a plurality of local voltage regulators each including a first input, a second input, and an output; a transconductance amplifier connected with the local voltage regulators and configured to drive the local voltage regulators, including a first input, a second input and an output; a reference voltage source; and a plurality of transistors. The output of the transconductance amplifier is connected to the first input of each local voltage regulators. The first input of each local voltage regulator is connected to ground through a first capacitor. The output of each local voltage regulator is connected to gate of each transistor correspondingly. Source or drain of each transistor is connected to a load, to the second input of the local voltage regulator, to each other through a plurality of first resistors representing metal routing resistance, and to ground through a RC network.

Abstract: The disclosed switching regulator, including a controller for a switching regulator, is adaptable to supplying, or controlling the supply of, regulated current to a load that is isolated from a source of input power by a flyback transformer, and includes: (a) detecting, after transistor SWOFF, a zero crossing ZCD corresponding to a primary side switching node voltage VSW decreasing to the input voltage Vin, which occurs after a secondary current IS is substantially zero and before the next SWON; (c) establishing a time-integral window T-I_W with a leading edge corresponding to SWOFF and a trailing edge corresponding to ZCD; and (d) modulating at least the time SWOFF relative to SWON based on the primary peak current IPP at SWOFF and the time-integral window, such that a regulated load current is supplied to the load.

Abstract: A method includes receiving a variable reference voltage at a power converter and generating a regulated output voltage based on the variable reference voltage. The method also includes sequentially driving multiple sets of light emitting diodes (LEDs) using the regulated output voltage, where each set includes at least one LED. The variable reference voltage varies based on the set of LEDs being driven. For example, the method could include receiving a first reference voltage, generating a first output voltage based on the first reference voltage, and driving a first set of LEDs using the first output voltage. The method could then include receiving a second reference voltage, generating a second output voltage based on the second reference voltage, and driving a second set of LEDs using the second output voltage. At least one additional set of LEDs could be driven concurrently with the sequential driving of the multiple sets of LEDs.

Abstract: A system includes multiple dynamic current equalizers (DCEs). Each DCE includes a first control loop configured to regulate a current through a circuit branch associated with the dynamic current equalizer. The first control loop includes a first amplifier having two inputs. Each DCE also includes a second control loop configured to regulate a control signal. The second control loop includes a second amplifier having two inputs coupled to the inputs of the first amplifier. The first amplifier has an input offset compared to the second amplifier. The DCEs are configured such that one DCE regulates the control signal while one or more other DCEs regulate the currents through the associated circuit branches based on the control signal. The DCEs can be configured to achieve one or more ratios between multiple currents flowing through multiple circuit branches, where the one or more ratios are defined by resistances coupled to the DCEs.

Abstract: A method includes receiving a variable reference voltage at a power converter and generating a regulated output voltage based on the variable reference voltage. The method also includes sequentially driving multiple sets of light emitting diodes (LEDs) using the regulated output voltage, where each set includes at least one LED. The variable reference voltage varies based on the set of LEDs being driven. For example, the method could include receiving a first reference voltage, generating a first output voltage based on the first reference voltage, and driving a first set of LEDs using the first output voltage. The method could then include receiving a second reference voltage, generating a second output voltage based on the second reference voltage, and driving a second set of LEDs using the second output voltage. At least one additional set of LEDs could be driven concurrently with the sequential driving of the multiple sets of LEDs.

Abstract: A system includes multiple dynamic current equalizers (DCEs). Each DCE includes a first control loop configured to regulate a current through a circuit branch associated with the dynamic current equalizer. The first control loop includes a first amplifier having two inputs. Each DCE also includes a second control loop configured to regulate a control signal. The second control loop includes a second amplifier having two inputs coupled to the inputs of the first amplifier. The first amplifier has an input offset compared to the second amplifier. The DCEs are configured such that one DCE regulates the control signal while one or more other DCEs regulate the currents through the associated circuit branches based on the control signal. The DCEs can be configured to achieve one or more ratios between multiple currents flowing through multiple circuit branches, where the one or more ratios are defined by resistances coupled to the DCEs.

Abstract: A regulator circuit and a method of generating a stable, low-ripple output, step-up or step-down voltage are disclosed. A low ESR (Equivalent Series Resistance) output capacitor is employed to provide low output voltage ripple. A voltage, ?VESRi, is generated using information based on an input voltage and the output voltage. ?VESRi is coupled onto an intermediate reference voltage generated by an integrator based on the output voltage and a constant reference voltage, to form another voltage, VREFi. VREFi is coupled to an input of a feedback comparator, instead of a plain constant reference voltage, to modulate the duty cycle of a main switch. The output voltage is inputted as a feedback signal to another input of the feedback comparator. ?VESRi, is generated using information based on an input voltage and the output voltage in such a way that output voltage is stable without sub-harmonic oscillation.

Abstract: A system and method are disclosed for providing a pulsating current output having ultra fast rise and fall times. A linear constant current controller is provided that comprises an operational amplifier. A compensation capacitor is connected to an output of the operational amplifier through a switch circuit. The switch circuit closes to initially charge up the compensation capacitor. The switch circuit then opens to isolate the compensation capacitor when the output of the operational amplifier is connected to ground. A value of voltage is maintained on the compensation capacitor so that the compensation capacitor does not need to be recharged for each subsequent cycle of the pulsating current output. The linear constant current controller is capable of generating a pulsating output current that has rise and fall times in the tens of nanoseconds.

Abstract: A projected on-time (POT) switching regulator is provided. The regulator includes a switching regulator controller and a main switch. The controller includes a feedback comparator and an on-timer. The feedback comparator compares the output voltage to a reference voltage. Whenever the feedback comparator trips, the main switch is turned on, and the on-timer controls the turn-on duration (on-time) of the main switch, where the duration is adjusted by the input and output voltages according to a preset transfer function. The transfer function is applicable to both CCM and DCM operation. However, during CCM mode operation, at least above a minimum on-time, the on-time is adjusted so that the switching frequency of the regulator is approximately constant. The on-timer includes a comparator that compares an adjustable voltage VFQ to a ramp voltage VIFQ generated by providing an adjustable current IFQ to a capacitor CREF.

Abstract: A constant on-time regulator that may use a capacitor with low ESR without needing a series resistor is provided. A capacitor is employed to AC-couple a current sense voltage into the reference signal to provide a modified reference signal. The comparator compares the feedback voltage with the modified reference signal rather than a constant reference signal. Also, a switch may be included between the current sense voltage and the reference signal to improve load regulation.

Abstract: An apparatus in an electronic device such as a buck converter circuit receives as a first input a voltage signal VSNS from the electronic device that represents a current through the electronic device, and receives as a second input a direct current reference voltage signal from a reference voltage source VREF. The apparatus regulates a direct current output IOUT of the electronic device with respect to the reference voltage source VREF by applying a pulse level transformation to the voltage signal VSNS using an operational transconductance amplifier.

Abstract: A constant on-time regulator that may use a capacitor with low ESR without needing a series resistor is provided. A capacitor is employed to AC-couple a current sense voltage into the reference signal to provide a modified reference signal. The comparator compares the feedback voltage with the modified reference signal rather than a constant reference signal.

Abstract: A switch control (12) circuit which optimizes the efficiency of a buck or boost converter by eliminating simultaneous conductive states of the main power transistor (16) and the synchronous rectifying transistor (18). Power dissipation of the synchronous rectifying transistor (18) is minimized by reducing the amount of time (Td1 and Td2) that the intrinsic body diode of transistor (18) conducts current. Charge control circuit (53) is utilized for boost converter operation and charge control circuit (118) is utilized for buck converter operation.

Abstract: DC to DC boost converters (10 and 54) utilize boost controllers (12 and 28) which provide multifunctional IC pins (LB/{overscore (SHDN)} and FB/{overscore (SHDN)}) . Boost controller (12) allows the combination of a low battery sense function and an IC shutdown function to be implemented with a single pin (LB/{overscore (SHDN)}) . Boost controller (28) allows the combination of an output voltage feedback function and an IC shutdown function to be implemented with a single pin (FB/{overscore (SHDN )}). DC to DC boost controllers (12 and 28) facilitate smaller package sizes due to the reduction of I/O pins required.

Abstract: A switch control (12) circuit which optimizes the efficiency of a buck or boost converter by eliminating simultaneous conductive states of the main power transistor (16) and the synchronous rectifying transistor (18). Power dissipation of the synchronous rectifying transistor (18) is minimized by reducing the amount of time (Td1 and Td2) that the intrinsic body diode of transistor (18) conducts current. Charge control circuit (53) is utilized for boost converter operation and charge control circuit (118) is utilized for buck converter operation.

Abstract: A circuit (100) for produces an LCD contrast voltage signal (VLCD) for a low power MCU-controlled application. The reference voltage (VREF) for a switched mode power supply circuit (210) is supplied by a circuit comprising: logic control circuitry (110) for receiving MCU commands, a counter (120), a digital-to-analog converter (130), and a transmission gates (140, 150) and capacitors (160, 180) for generating the SMPS reference voltage (VREF), and a comparator to set off a recharge cycle whenever the capacitors' voltage difference is more than a pre-set offset voltage. This circuit has lower quiescent power consumption since, in idle cycle, only the comparator (200) consumes quiescent current which can be less than 1 .mu.A.