Patents by Inventor Hoki Kim
Hoki Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7023758Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.Type: GrantFiled: August 17, 2005Date of Patent: April 4, 2006Assignee: International Business Machines CorporationInventors: David R. Hanson, Gregory J Fredeman, John W. Golz, Hoki Kim, Paul C. Parries
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Publication number: 20060039226Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.Type: ApplicationFiled: August 17, 2005Publication date: February 23, 2006Inventors: David Hanson, Gregory Fredeman, John Golz, Hoki Kim, Paul Parries
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Patent number: 6990025Abstract: A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors.Type: GrantFiled: August 29, 2003Date of Patent: January 24, 2006Assignee: International Business Machines CorporationInventors: Toshiaki Kirihata, Hoki Kim, Matthew Wordeman
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Patent number: 6954387Abstract: In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.Type: GrantFiled: July 15, 2003Date of Patent: October 11, 2005Assignee: International Business Machines CorporationInventors: Hoki Kim, Toshiaki Kirihata, David R. Hanson, Gregory J. Fredeman, John Golz
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Patent number: 6950353Abstract: A memory array includes a true bitline and a complementary bitline and a sense amplifier connected thereto; a row of normal cells with capacitors for data storage and bitline storage capacitors. A row of dummy cells with dummy cell capacitors is also provided. A clock provides wordline drive signals to the normal cells. When operating in the test mode, the clock provides at least one dummy wordline drive signal to the dummy cell switch in response to a testing signal for connecting the dummy cell capacitor to the bitline. A plurality of rows of dummy cells can be employed with various permutations of actuation thereof to provide various levels of capacitance connected to the bitlines in the test mode.Type: GrantFiled: February 1, 2005Date of Patent: September 27, 2005Assignee: International Business Machines CorporationInventors: Hoki Kim, Toshiaki Kirihata
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Patent number: 6947348Abstract: A method is provided for accessing a storage cell of a dynamic random access memory (DRAM) having an array of gain cells being read accessible by a read wordline and a read bitline, and being write accessible by a write wordline and write bitline separate from said read wordline and read bitline. The method includes activating a read wordline of the array of gain cells to permit signals from a plurality of gain cells coupled to the read wordline to develop on a plurality of corresponding read bitlines coupled to the gain cells. An interlock signal is then generated in the DRAM after activating the read wordline. The read wordline is then deactivated in response to the interlock signal.Type: GrantFiled: July 15, 2003Date of Patent: September 20, 2005Assignee: International Business Machines CorporationInventors: Hoki Kim, Toshiaki Kirihata
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Patent number: 6891389Abstract: A method for detecting quiescent current in an integrated circuit is provided that includes detecting a magnetic field generated by the quiescent current and in response generating a magnetic field signal that is indicative of the detected magnetic field. The magnetic field signal is then amplified and converted into a differential voltage signal. The differential voltage signal is then converted into a digital format.Type: GrantFiled: November 30, 2001Date of Patent: May 10, 2005Assignee: The Texas A&M University SystemInventors: Duncan M. Walker, Hoki Kim
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Publication number: 20050047218Abstract: A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors.Type: ApplicationFiled: August 29, 2003Publication date: March 3, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiaki Kirihata, Hoki Kim, Matthew Wordeman
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Publication number: 20050024923Abstract: A method is provided for accessing a storage cell of a dynamic random access memory (DRAM) having an array of gain cells being read accessible by a read wordline and a read bitline, and being write accessible by a write wordline and write bitline separate from said read wordline and read bitline. The method includes activating a read wordline of the array of gain cells to permit signals from a plurality of gain cells coupled to the read wordline to develop on a plurality of corresponding read bitlines coupled to the gain cells. An interlock signal is then generated in the DRAM after activating the read wordline. The read wordline is then deactivated in response to the interlock signal.Type: ApplicationFiled: July 15, 2003Publication date: February 3, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hoki Kim, Toshiaki Kirihata
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Publication number: 20050013185Abstract: In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.Type: ApplicationFiled: July 15, 2003Publication date: January 20, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hoki Kim, Toshiaki Kirihata, David Hanson, Gregory Fredeman, John Golz
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Publication number: 20040252573Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.Type: ApplicationFiled: June 16, 2003Publication date: December 16, 2004Applicant: International Business Machine CorporationInventors: David R. Hanson, Gregory J. Fredeman, John W. Golz, Hoki Kim, Paul C. Parries
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Publication number: 20040240246Abstract: As disclosed herein, an integrated circuit memory is provided which includes primary sense amplifiers coupled for access to a multiplicity of storage cells, second sense amplifiers, and pairs of input/output data lines (IODLs), each IODL pair being coupled to a primary sense amplifier, and each IODL pair carrying complementary signals representing a storage bit. The memory further includes pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier and each BPDL pair being adapted to carry other complementary signals representing a storage bit. Local buffers are adapted to transfer, in accordance with control input, the complementary signals carried by the IODLs to the BPDLs, and vice versa.Type: ApplicationFiled: May 29, 2003Publication date: December 2, 2004Inventors: John W. Golz, David R. Hanson, Hoki Kim
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Patent number: 6816397Abstract: As disclosed herein, an integrated circuit memory is provided which includes primary sense amplifiers coupled for access to a multiplicity of storage cells, second sense amplifiers, and pairs of input/output data lines (IODLs), each IODL pair being coupled to a primary sense amplifier, and each IODL pair carrying complementary signals representing a storage bit. The memory further includes pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier and each BPDL pair being adapted to carry other complementary signals representing a storage bit. Local buffers are adapted to transfer, in accordance with control input, the complementary signals carried by the IODLs to the BPDLs, and vice versa.Type: GrantFiled: May 29, 2003Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: John W. Golz, David R. Hanson, Hoki Kim
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Patent number: 6768143Abstract: An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.Type: GrantFiled: August 26, 2003Date of Patent: July 27, 2004Assignee: International Business Machines CorporationInventors: Gregory J. Fredeman, John W. Golz, David R. Hanson, Hoki Kim