Abstract: Disclosed are a thermoelectric generation apparatus, a heat generation apparatus for fuel storage tanks, and a waste heat recovery system. The thermoelectric generation apparatus according to an embodiment of this disclosure includes a first piping through which a fluid flows, a second piping through which a cooling medium of a lower temperature than the fluid flows so as to radiate the heat of the fluid, a plurality of first radiating fins having one side in contact with air of a lower temperature than the fluid so as to radiate the heat of the fluid and the other side in contact with the second piping, and a thermoelectric generation module provided between the first piping and the second piping to produce electricity through a temperature difference between the first piping and the second piping.

Abstract: Disclosed are a thermoelectric generation apparatus, a heat generation apparatus for fuel storage tanks, and a waste heat recovery system. The thermoelectric generation apparatus according to an embodiment of this disclosure includes a first piping through which a fluid flows, a second piping through which a cooling medium of a lower temperature than the fluid flows so as to radiate the heat of the fluid, a plurality of first radiating fins having one side in contact with air of a lower temperature than the fluid so as to radiate the heat of the fluid and the other side in contact with the second piping, and a thermoelectric generation module provided between the first piping and the second piping to produce electricity through a temperature difference between the first piping and the second piping.

Abstract: Provided are a thermoelectric power generation module, a thermoelectric power generation apparatus including the same, an anti-icing vaporization device including the same, and an apparatus for a vaporized fuel gas liquefaction process including the same. The thermoelectric power generation module includes: a pipe through which a fluid flows; and a thermoelectric power generator configured to surround the pipe and to produce power due to a temperature difference between the fluid and outside air.

Abstract: A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines.

Abstract: A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines.

Abstract: A method of controlling process distribution of a semiconductor process includes receiving process distribution data representing the process distribution of the semiconductor process, receiving a parameter related to the process distribution, generating a virtual metrology model corresponding to the process distribution based on a relationship between the process distribution data and the parameter, and modifying a process variable affecting the process distribution based on the virtual metrology model.

Abstract: A semiconductor memory device includes conductive patterns vertically stacked on the substrate and having pad regions extended further at edge portions of the conductive patterns as the conductive patterns descend from an uppermost conductive pattern to a lowermost conductive pattern, a first contact plug disposed on a first pad region of the lowermost conductive pattern, a buffer conductive pattern disposed on a second pad region positioned above the first pad region, and a second contact plug formed on the buffer conductive pattern.

Abstract: In one example embodiment, a method of maintaining a semiconductor manufacturing line includes setting up a recipe for controlling an implementation of a unit process based on which at least one semiconductor device is manufactured by a manufacturing facility. The method further includes collecting reference data of the manufacturing facility being controlled according to the reference recipe and obtaining a statistical model of the reference data and a health index of the statistical model, the health index being a limit beyond which an output of the semiconductor manufacturing line decreases. The method further includes controlling the implementation of the unit process and obtaining monitoring data during the implementation of the unit process using the statistical mode. The method further includes renewing the statistical model based on the monitoring data.

Abstract: A semiconductor device may include a contact mold layer on a substrate, the contact mold layer defining first and second contact portions on the substrate, a wire mold layer on the contact mold layer, and first and second wires penetrating the wire mold layer and extending in a first direction, the first and second wires contacting the respective first and second contact portions and the contact mold layer. The first and second wires may be arranged in an alternating manner, and the first and second contact portions may be arranged to have a zigzag configuration. Each of the first and second contact portions may include a conductive pattern and a barrier pattern, and the barrier pattern may have a top surface lower than a top surface of the contact mold layer.

Abstract: A semiconductor memory device includes conductive patterns vertically stacked on the substrate and having pad regions extended further at edge portions of the conductive patterns as the conductive patterns descend from an uppermost conductive pattern to a lowermost conductive pattern, a first contact plug disposed on a first pad region of the lowermost conductive pattern, a buffer conductive pattern disposed on a second pad region positioned above the first pad region, and a second contact plug formed on the buffer conductive pattern.

Abstract: In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

Abstract: Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes.

Abstract: Provided are methods of forming a contact plug of a semiconductor device. Methods of forming a contact plug of a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate on which a lower structure is formed, forming a contact hole in the interlayer insulating layer, the contact hole exposing the lower structure, and forming a W layer and then a WN layer to form a W/WN barrier layer in the contact hole. Methods may include H2 remote plasma treating the W/WN barrier layer, forming a W-plug on the H2 remote plasma treated W/WN barrier layer to fill the contact hole, and chemical mechanical polishing (CMP) the W-plug and then the W/WN barrier layer in order to expose the interlayer insulating layer.

Abstract: An apparatus and method for fabricating semiconductor devices may increase reliability of the semiconductor devices by decreasing generation of particles and enhancing operation efficiency by decreasing the number of cleanings. The apparatus may include a chamber having a cover plate, susceptors for securely placing semiconductor substrates within the chamber, shower heads located on the cover plate to supply reaction gases into the chamber, and a curtain gas line connected to the cover plate to supply heated curtain gases between the shower heads.

Abstract: A method of controlling process distribution of a semiconductor process includes receiving process distribution data representing the process distribution of the semiconductor process, receiving a parameter related to the process distribution, generating a virtual metrology model corresponding to the process distribution based on a relationship between the process distribution data and the parameter, and modifying a process variable affecting the process distribution based on the virtual metrology model.

Abstract: In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

Abstract: In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

Abstract: A method of monitoring a semiconductor process is provided. The method includes preparing a process chamber including first and second electrodes spaced apart from and facing each other, and connecting the first electrode to a ground and connecting the second electrode to a radio frequency power source. An impedance in the process chamber is measured using a voltage value and a current value at the second electrode. The consumption amount of consumables in the process chamber is checked using the impedance. Varied process conditions are adjusted within an initial set range.

Abstract: A method of calculating a thickness of a layer may include forming the layer on a substrate in a chamber, measuring optical emission spectrum data from the chamber, and calculating the thickness of the layer from the optical emission spectrum data. A method of forming a layer may include depositing the layer on a substrate in a chamber, measuring optical emission spectrum data from the chamber, calculating a thickness of the layer using the optical emission spectrum data, and ending the depositing of the layer when the calculated thickness of the layer is within a target thickness range.

Abstract: Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes.