Abstract: A computer system may include a processor; a first memory device; a second memory device; a cache memory including a plurality of cache entries and a cache controller. The cache controller is configured to manage a source indicating whether a caching data is provided from the first memory device or the second memory device, and determine a cache entry to be evicted from the cache entries based on a cache miss ratio of request data by the source which the request data is read when the request data of the processor do not exist in the cache memory and a cache occupancy ratio by the source.

Abstract: A pooled memory device includes plural memory devices and a controller. The plural memory devices include a first memory and a second memory with at least one power supply configured to control power supplied to each of the plural memory devices. The controller is coupled to an interconnect device which is configured to provide the plural memory devices to at least one external device as a logical device. The controller is configured to track available storage capacities of the first memory and the second memory and cut off power supplied to an unused memory among the first memory and the second memory.

Abstract: A memory system may include a first cache memory including a plurality of regions, which are accessed using a first address, and in each of which an indication of whether cached data is present and a second address are stored. A memory system may also include a second cache memory configured to be accessed using the second address stored in an accessed region of the first cache memory when, as a result of an access of the first cache memory, cached data is present. Still further, a memory system may include a main memory configured to be accessed using the first address when, as the result of the access of the first cache memory, cached data is not present.

Abstract: An on-chip logic block may include a host ECC circuit configured to correct an error based on host parity. The on-chip logic block may include a memory ECC circuit configured to correct an error based on memory parity.

Abstract: A stack chip package may include a plurality of stacked semiconductor chips. Each of the semiconductor chips may have a first node, a second node, a third node and a fourth node corresponding to corners of the semiconductor chip. The plurality of semiconductor chips may be sequentially stacked such that, when a semiconductor chip is disposed directly on another semiconductor chip, the first node of the semiconductor chip is positioned over a side between the first node and the second node of the another semiconductor chip.

Abstract: A memory device includes: a main block that includes a plurality of first pages that are accessible based on a multi-bit address; and a sub-block that includes a plurality of second pages that are accessible based on a portion of bits of the multi-bit address, and stores a replacement data for replacing entire or a portion of the data of an accessed first page among the plurality of the first pages in a second page that stores the same tags as the other bits of the multi-bit address among the accessed second pages.

Abstract: A stack chip package may include a plurality of stacked semiconductor chips. Each of the semiconductor chips may have a first node, a second node, a third node and a fourth node corresponding to corners of the semiconductor chip. The plurality of semiconductor chips may be sequentially stacked such that, when a semiconductor chip is disposed directly on another semiconductor chip, the first node of the semiconductor chip is positioned over a side between the first node and the second node of the another semiconductor chip.

Abstract: A memory device includes: a main block that includes a plurality of first pages that are accessible based on a multi-bit address; and a sub-block that includes a plurality of second pages that are accessible based on a portion of bits of the multi-bit address, and stores a replacement data for replacing entire or a portion of the data of an accessed first page among the plurality of the first pages in a second page that stores the same tags as the other bits of the multi-bit address among the accessed second pages.

Abstract: A memory system may include a first cache memory including a plurality of regions, which are accessed using a first address, and in each of which an indication of whether cached data is present and a second address are stored. A memory system may also include a second cache memory configured to be accessed using the second address stored in an accessed region of the first cache memory when, as a result of an access of the first cache memory, cached data is present. Still further, a memory system may include a main memory configured to be accessed using the first address when, as the result of the access of the first cache memory, cached data is not present.

Abstract: An on-chip logic block may include a host ECC circuit configured to correct an error based on host parity. The on-chip logic block may include a memory ECC circuit configured to correct an error based on memory parity.