Abstract: A method for an improved characterization of standard cells in a circuit design process is disclosed. Adaptive body biasing is considered during the design process by using simulation results of a cell set, a data-set for performance of the cell set, and a data-set for a hardware performance for a slow, typical and fast circuit property. Static deviations in a supply voltage are considered by determining a reference performance of a cell and a reference hardware performance monitor value at a PVT corner. A virtual regulation and adapting of body bias voltages of the cell set is performed such that the reference performance of the cell or the reference hardware performance monitor value will be reached at each PVT corner and for compensating the static deviation in the supply voltage. The results are provided in a library file.

Abstract: A method for an improved characterization of standard cells in a circuit design process is disclosed. Adaptive body biasing is considered during the design process by using simulation results of a cell set, a data-set for performance of the cell set, and a data-set for a hardware performance for a slow, typical and fast circuit property. Static deviations in a supply voltage are considered by determining a reference performance of a cell and a reference hardware performance monitor value at a PVT corner. A virtual regulation and adapting of body bias voltages of the cell set is performed such that the reference performance of the cell or the reference hardware performance monitor value will be reached at each PVT corner and for compensating the static deviation in the supply voltage. The results are provided in a library file.

Abstract: By providing at least two hardware representations of a specified circuit design, an efficient debugging system is provided that allows 100% design visibility at an extremely reduced simulation time owing to a time-shifted operation of the at least two hardware representations. Upon detection of a specified abort state in the leading hardware representation, the corresponding delayed state of the time-shifted hardware representation may be used for a subsequent simulation of only a relevant portion of the test run that has lead to the specified abort state.

Abstract: By providing at least two hardware representations of a specified circuit design, an efficient debugging system is provided that allows 100% design visibility at an extremely reduced simulation time owing to a time-shifted operation of the at least two hardware representations. Upon detection of a specified abort state in the leading hardware representation, the corresponding delayed state of the time-shifted hardware representation may be used for a subsequent simulation of only a relevant portion of the test run that has lead to the specified abort state.