Abstract: A circuit arrangement for generating an electronically controlled electrical resistance by apparatus of at least one MOS transistor. A source-drain junction of the MOS transistor is used for the generation of the electrical resistance between a first and a second terminal, in order to optimize the linearity of the electrical resistance, there have been provided means for generating a bulk signal, which apparatus generate from the voltage on that terminal of the circuit arrangement which is coupled to the source electrode of an associated MOS transistor a signal for driving a bulk electrode of the associated MOS transistor, which signal is generated from the voltage on the terminal and an additionally superposed direct voltage of such a polarity that, depending on the doping type of the MOS transistor the formation of a diode between the source and bulk regions of this MOS transistor is avoided.

Abstract: A filter circuit is provided that provides an input impedance arrangement with a high impedance value, which can be fabricated on a semiconductor body with a high accuracy and with a minimal semiconductor area being required. The input impedance arrangement comprises at least one T network having at least three impedance branches, of which a first impedance branch is connected to the filter input, a second impedance branch is connected to the amplifier input and a third impedance branch is connected to a circuit point for draining a current from the filter input.

Abstract: For varying the filter frequencies in an integrator-filter circuit for filtering a push-pull signal by at least two integrator signal filters (31, 32, 33) having integrator elements (1), whose filter frequencies are adjustable by control currents (I.sub.n,1, I.sub.n,2) applied to the integrator elements (1), the integrator-filter circuit includes a reference integrator filter (38) having at least two integrator elements (1) constructed in an identical technique as the other integrator elements (1). This reference integrator filter, when tuned to the frequency of a test signal applied thereto, shifts the phase of the test signal by a defined value, and is arranged subsequent to a phase comparator (39) which also receives the test signal, so that a correction signal is derived from the output signal of the phase comparator (39), in dependence upon this correction signal. The control currents (I.sub.n,1, I.sub.

Abstract: To achieve a constant control range in an integrator-filter circuit for filtering a push-pull signal, having at least two integrator elements (1) this second control current being having resistors (11, 12) arranged at its inputs, a subsequent current multiplier (13) having two signal inputs (14, 15) and preceding a push-pull amplifier (18) with an inverting input (20) and a non-inverting input (19), having inverting output (21) fed back to the non-inverting input (19) and a non-inverting output (23) fed back to the inverting input (20) via capacitances (22, 24), the current multiplier (13) receiving, at two control inputs (37, 38), a first and a second control current (I.sub.1, I.sub.2) for adjusting the integration time constant of the integrator element (1) is adjustable and from which the second control current (I.sub.2) flows in substantially two halves through the signal inputs (14, 15) of the current multiplier (13), an associated third control current (I.sub.

Abstract: A circuit arrangement for supplying a constant current which is stabilized against temperature variations. The constant current is produced by a current source which is controlled by a control stage in which a first control current is supplied to each of a first and a second resistor, at least one of which is trimmable. The first control current is controlled so that the difference between the voltages produced thereby across the first and second resistors is in a first predetermined ratio to the constant voltage produced by a reference voltage source. The current source is controlled by the control stage so that the constant current produced thereby is in a second predetermined ratio to the first control currents.

Abstract: A circuit arrangement which includes an FM demodulator having a delay circuit which subjects the received FM signal to a preset time delay and a signal combining circuit which combines the delayed and undelayed FM signal to derive a combined signal the mean value of which is proportional to the frequency of the FM signal. A low pass filter derives the demodulated signal from such combined signal. The proportionality factor is determined by the preset time delay, which is controllable by a control signal supplied to the delay circuit by a datum level detector which detects a selected datum level of the demodulated signal; for example, the lowest level of such signal. By controlling the time delay in accordance with such datum level, the datum level detector thereby stabilizes the maximum amplitude of the demodulated signal relative to the datum level thereof despite variations in the maximum frequency swing of the received FM signal.