Abstract: A digital filter converts a digital input sequence into a digital output sequence. The digital filter includes an integrator stage having a plurality of closed-loop controlled time-delay elements. The integrator stage is configured to have each closed-loop controlled time-delay element set to a value which is predetermined for the respective closed-loop controlled time-delay element. The digital filter includes a further stage. The integrator stage and the further stage are configured to operate at different clock frequencies.

Abstract: The transfer function of a filter processing unit is defined by a set of filter coefficients that are continually updated in a coefficient-updating unit. The level of the output signal is adjusted by a level-adjustment unit where, if the largest filter coefficient exceeds an upper threshold value or is below a lower threshold value, a comparator outputs control signals to coefficient-based shifters and to a data signal shifter such that these shift their applied bit sequences in opposite directions and thus multiply or divide the applied data signals by a factor?2.

Abstract: A digital filter converts a digital input sequence into a digital output sequence. The digital filter includes an integrator stage having a plurality of closed-loop controlled time-delay elements. The integrator stage is configured to have each closed-loop controlled time-delay element set to a value which is predetermined for the respective closed-loop controlled time-delay element. The digital filter includes a further stage. The integrator stage and the further stage are configured to operate at different clock frequencies.

Abstract: A digital comb filter contains filter stages. Each filter stage has a latch disposed at a filter stage input, which latch, by outputting each input data value twice in each case doubles the sampling rate. Each filter stage further has a filter structure, a partial transfer function {overscore (H)} (z) of which is {overscore (H)}(z)?(1+z?1)k?1, where k is an order of the filter device and z?1 is the z transform of a delay by one sampling pulse. The implementation according to the invention does not require an error correction circuit.

Abstract: In a method for determining the interference power in a CDMA radio receiver, once a received signal has been despread, the interference power of the despread signal is determined by comparing received symbols with symbols that are known a-priori to the receiver and with received and determined data symbols that are not known a-priori to the receiver.

Abstract: The transfer function of a filter processing unit is defined by a set of filter coefficients that are continually updated in a coefficient-updating unit. The level of the output signal is adjusted by a level-adjustment unit where, if the largest filter coefficient exceeds an upper threshold value or is below a lower threshold value, a comparator outputs control signals to coefficient-based shifters and to a data signal shifter such that these shift their applied bit sequences in opposite directions and thus multiply or divide the applied data signals by a factor≧2.

Abstract: A digital comb filter contains filter stages. Each filter stage has a latch disposed at a filter stage input, which latch, by outputting each input data value twice in each case doubles the sampling rate. Each filter stage further has a filter structure, a partial transfer function {overscore (H)}(z) of which is {overscore (H)}(z)&agr;(1+z−1)k−1, where k is an order of the filter device and z−1 is the z transform of a delay by one sampling pulse. The implementation according to the invention does not require an error correction circuit.