Patents by Inventor Hollie Reed

Hollie Reed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sacrificial Compositions And Methods Of Fabricating A Structure Using Sacrificial Compositions
    Publication number: 20090120905
    Abstract: Compositions, methods of use thereof, and methods of decomposition thereof, are provided. One exemplary composition, among others, includes a polymer and a catalytic amount of a negative tone photoinitiator.
    Type: Application
    Filed: November 18, 2008
    Publication date: May 14, 2009
    Applicant: GEORGIA TECH RESEARCH CORPORATION
    Inventors: Paul A. Kohl, Paul Jayachandran Joseph, Hollie Reed, Sue Bidstrup-Allen, Celesta E. White, Clifford Henderson
  • Sacrificial Compositions And Methods Of Fabricating A Structure Using Sacrificial Compositions
    Publication number: 20090107952
    Abstract: Compositions, methods of use thereof, and methods of decomposition thereof, are provided. One exemplary composition, among others, includes a polymer and a catalytic amount of a negative tone photoinitiator.
    Type: Application
    Filed: November 18, 2008
    Publication date: April 30, 2009
    Applicant: Georgia Tech Research Corporation
    Inventors: Paul A. Kohl, Paul Jayachandran Joseph, Hollie Reed, Sue Bidstrup-Allen, Celesta E. White, Clifford Henderson
  • Sacrificial compositions and methods of fabricating a structure using sacrificial compositions
    Patent number: 7459267
    Abstract: Compositions, methods of use thereof, and methods of decomposition thereof, are provided. One exemplary composition, among others, includes a polymer and a catalytic amount of a negative tone photoinitiator.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: December 2, 2008
    Assignee: Georgia Tech Research Corporation
    Inventors: Paul A. Kohl, Paul Jayachandran Joseph, Hollie Reed, Sue Bidstrup-Allen, Celesta E. White, Clifford Henderson
  • Sacrificial compositions and methods of fabricating a structure using sacrificial compositions
    Publication number: 20060263718
    Abstract: Compositions, methods of use thereof, and methods of decomposition thereof, are provided. One exemplary composition, among others, includes a polymer and a catalytic amount of a negative tone photoinitiator.
    Type: Application
    Filed: April 5, 2006
    Publication date: November 23, 2006
    Inventors: Paul Kohl, Paul Joseph, Hollie Reed, Sue Bidstrup-Allen, Celesta White, Clifford Henderson
  • Sacrificial compositions, methods of use thereof, and methods of decomposition thereof
    Patent number: 7052821
    Abstract: Polymers, methods of use thereof, and methods of decomposition thereof, are provided. One exemplary polymer, among others, includes, a composition having a sacrificial polymer and a photoacid generator.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: May 30, 2006
    Assignee: Georgia Tech Research Corporation
    Inventors: Paul A. Kohl, Paul Jayachandran Joseph, Hollie Reed, Sue Bidstrup-Allen, Celesta E. White, Clifford Henderson
  • Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package
    Patent number: 6954576
    Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: October 11, 2005
    Assignee: Georgia Tech Research Corporation
    Inventors: Tony Mule′, Chirag Patel, James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Kevin P. Martin, Stephen M. Schultz, Muhannad Bakir, Hollie Reed, Paul Kohl
  • Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package
    Publication number: 20040264840
    Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
    Type: Application
    Filed: July 21, 2004
    Publication date: December 30, 2004
    Inventors: Tony Mule, Chirag Patel, James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Kevin P. Martin, Stephen M. Schultz, Muhannad Bakir, Hollie Reed, Paul Kohl
  • Backplane, printed wiring board, and/or multi-chip module-level optical interconnect layer having embedded air-gap technologies and methods of fabrication
    Patent number: 6788867
    Abstract: Optical interconnect layers and methods of fabrication thereof are described. In addition, the optical interconnect layers integrated into devices such as backplane (BP), printed wiring board (PWB), and multi-chip module (MCM) level devices are described. A representative optical interconnect layer includes a first cladding layer, a second cladding layer, one or more waveguides having a waveguide core and an air-gap cladding layer engaging a portion of waveguide core, wherein the first cladding layer and the second cladding layer engage the waveguide.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: September 7, 2004
    Assignee: Georgia Tech Research Corp.
    Inventors: Tony Mule′, James D. Meindl, Paul Kohl, Stephen M. Schultz, Thomas K. Gaylord, Elias N. Glytsis, Ricardo Villalaz, Muhannad Bakir, Hollie Reed
  • Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package
    Patent number: 6785458
    Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: August 31, 2004
    Assignee: Georgia Tech Research Corporation
    Inventors: Tony Mule′, Chirag Patel, James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Kevin P. Martin, Stephen M. Schultz, Muhannad Bakir, Hollie Reed, Paul Kohl
  • Sacrificial compositions, methods of use thereof, and methods of decomposition thereof
    Publication number: 20040146803
    Abstract: Polymers, methods of use thereof, and methods of decomposition thereof, are provided. One exemplary polymer, among others, includes, a composition having a sacrificial polymer and a photoacid generator.
    Type: Application
    Filed: October 31, 2003
    Publication date: July 29, 2004
    Inventors: Paul A. Kohl, Paul Jayachandran Joseph, Hollie Reed, Sue Bidstrup-Allen, Celesta E. White, Clifford Henderson
  • Backplane, printed wiring board, and/or multi-chip module-level optical interconnect layer having embedded air-gap technologies and methods of fabrication
    Publication number: 20040126076
    Abstract: Optical interconnect layers and methods of fabrication thereof are described. In addition, the optical interconnect layers integrated into devices such as backplane (BP), printed wiring board (PWB), and multi-chip module (MCM) level devices are described. A representative optical interconnect layer includes a first cladding layer, a second cladding layer, one or more waveguides having a waveguide core and an air-gap cladding layer engaging a portion of waveguide core, wherein the first cladding layer and the second cladding layer engage the waveguide.
    Type: Application
    Filed: December 11, 2003
    Publication date: July 1, 2004
    Inventors: Tony Mule, James D. Meindl, Paul Kohl, Stephen M. Schultz, Thomas K. Gaylord, Elias N. Glytsis, Ricardo Villalaz, Muhannad Bakir, Hollie Reed
  • Compliant wafer-level packaging devices and methods of fabrication
    Patent number: 6690081
    Abstract: Devices and method of fabrication thereof are disclosed. A representative device includes one or more lead packages. The lead packages include a substrate including a plurality of die pads, an overcoat polymer layer, a plurality of sacrificial polymer layers disposed between the substrate and the overcoat polymer layer, and a plurality of leads. Each lead is disposed upon the overcoat polymer layer having a first portion disposed upon a die pad. The sacrificial polymer layer can be removed to form one or more air-gaps.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: February 10, 2004
    Assignee: Georgia Tech Research Corporation
    Inventors: Muhannad S. Bakir, Hollie Reed, Paul Kohl, Chirag S. Patel, Kevin P. Martin, James Meindl
  • Backplane, printed wiring board, and/or multi-chip module-level optical interconnect layer having embedded air-gap technologies and methods of fabrication
    Publication number: 20030012539
    Abstract: Optical interconnect layers and methods of fabrication thereof are described. In addition, the optical interconnect layers integrated into devices such as backplane (BP), printed wiring board (PWB), and multi-chip module (MCM) level devices are described. A representative optical interconnect layer includes a first cladding layer, a second cladding layer, one or more waveguides having a waveguide core and an air-gap cladding layer engaging a portion of waveguide core, wherein the first cladding layer and the second cladding layer engage the waveguide.
    Type: Application
    Filed: April 29, 2002
    Publication date: January 16, 2003
    Inventors: Tony Mule', James D. Meindl, Paul Kohl, Stephen M. Schultz, Thomas K. Gaylord, Elias N. Glytsis, Ricardo Villalaz, Muhannad Bakir, Hollie Reed
  • Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package
    Publication number: 20020136481
    Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
    Type: Application
    Filed: February 11, 2002
    Publication date: September 26, 2002
    Inventors: Tony Mule', Chirag Patel, James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Kevin P. Martin, Stephen M. Schultz, Muhannad Bakir, Hollie Reed, Paul Kohl
  • Compliant wafer-level packaging devices and methods of fabrication
    Publication number: 20020127768
    Abstract: Devices and method of fabrication thereof are disclosed. A representative device includes one or more lead packages. The lead packages include a substrate including a plurality of die pads, an overcoat polymer layer, a plurality of sacrificial polymer layers disposed between the substrate and the overcoat polymer layer, and a plurality of leads. Each lead is disposed upon the overcoat polymer layer having a first portion disposed upon a die pad. The sacrificial polymer layer can be removed to form one or more air-gaps.
    Type: Application
    Filed: November 19, 2001
    Publication date: September 12, 2002
    Inventors: Muhannad S. Badir, Hollie Reed, Paul Kohl, Chirag S. Patel, Kevin P. Martin, James Meindl