Abstract: An apparatus for storing information contained in a selected digital data signal comprises a selector. A first input terminal receives an operational digital data signal when the apparatus is operating in a normal mode, a second input terminal receives a shifted test data signal when the apparatus is operating in a maintenance mode, and a third input terminal is operatively connected to a signal having a constant reset state. The selector operatively connects one of the first, second, and third input terminals to the output terminal of the selector in response to a first and second control signal. A storage element, having a clock input terminal adapted to receive a clock signal and having a reset terminal adapted to receive a reset signal, stores the state present at the selected input terminal of the selector coincident with the clock signal.

Abstract: A test and maintenance system for use with a data processing system comprising a specialized circuit set wherein the circuit set registers can be configured into a serial array, a clock signal distribution system capable of delivering controlled clock signals to selected serial arrays, a maintenance data processor for providing predetermined signal groups, and addressing apparatus responsive to the predetermined signal groups for loading and unloading register arrays in response to the predetermined signals. The disclosed apparatus permits a predetermined signal group to be entered into the serial register array, a predetermined number of clock cycles (i.e. series of operations performed on the data), and the resulting signals shifted from the serial register array and signals applies to data processing unit for display or analysis.

Abstract: An arithmetic logic array employing soft-saturating current mode logic gates operates on pure binary data or binary coded decimal data. Two 4-bit data inputs are received along with a 5-bit Op code, a carry input, and decimal arithmetic operation signals. In response to a decimal add (DA) one data input is increased by a count of six, and in response to either a BCD add or a BCD subtract (DA + DS) the output is decreased by a count of six if no carry output is generated.

Abstract: A magnitude comparison circuit compares two X-bit binary numbers and two Y-bit binary numbers when a mode control signal is in a first condition and generates outputs indicating the relative magnitudes of the X-bit binary numbers and the Y-bit binary numbers. The magnitude comparison circuit compares two Z-bit binary numbers when the mode control signal is in a second condition and generates an output indicating the relative magnitude of the Z-bit binary numbers, where Z equals the sum of X and Y.