Abstract: An optical receiver with improved dynamic range may include at least one directional coupler having at least one input configured to couple to an optical fiber. The optical receiver may include a first signal path including a first photodetector coupled to an output of the at least one directional coupler, a first transimpedance amplifier (TIA) including an input coupled to the first photodetector, and an adder coupled to an output of the first TIA. The optical receiver may include a second signal path including a second photodetector coupled to an output of the at least one directional coupler, a second TIA including an input coupled to the second photodetector, and the adder coupled to an output of the second TIA. Further, the optical receiver may include an optical power sensing circuit coupled to at least one of the first TIA, the second TIA, and the adder.

Abstract: An optical receiver with improved dynamic range may include at least one directional coupler having at least one input configured to couple to an optical fiber. The optical receiver may include a first signal path including a first photodetector coupled to an output of the at least one directional coupler, a first transimpedance amplifier (TIA) including an input coupled to the first photodetector, and an adder coupled to an output of the first TIA. The optical receiver may include a second signal path including a second photodetector coupled to an output of the at least one directional coupler, a second TIA including an input coupled to the second photodetector, and the adder coupled to an output of the second TIA. Further, the optical receiver may include an optical power sensing circuit coupled to at least one of the first TIA, the second TIA, and the adder.

Abstract: An embodiment integrated circuit includes a first capacitive element including a first metal-oxide-semiconductor (MOS) capacitor and a second capacitive element coupled in parallel with the first capacitive element, where the second capacitive element includes a second MOS capacitor. Also, the integrated circuit includes a third capacitive element coupled in parallel with the first capacitive element and the second capacitive element, where the third capacitive element includes a first metal-insulator-metal (MIM) capacitor and a fourth capacitive element coupled in parallel with the first capacitive element, the second capacitive element, and the third capacitive element, where the fourth capacitive element includes a second MIM capacitor.

Abstract: An embodiment integrated circuit includes a first capacitive element including a first metal-oxide-semiconductor (MOS) capacitor and a second capacitive element coupled in parallel with the first capacitive element, where the second capacitive element includes a second MOS capacitor. Also, the integrated circuit includes a third capacitive element coupled in parallel with the first capacitive element and the second capacitive element, where the third capacitive element includes a first metal-insulator-metal (MIM) capacitor and a fourth capacitive element coupled in parallel with the first capacitive element, the second capacitive element, and the third capacitive element, where the fourth capacitive element includes a second MIM capacitor.

Abstract: Automatic gain control is provided in a sigma-delta analog-to-digital converter. The automatic gain control is entirely or partly provided by an amplifier and an attenuator within the sigma-delta analog-to-digital converter. The amplifier within the sigma-delta time continuous loop prior to quantization and an attenuator in the feedback prior to summation with incoming signals. Scaling within the sigma-delta analog-to-digital converter results in lower current requirements for automatic gain control without disturbing or minimizing disturbance of the stability of a sigma-delta topology. By providing at least part of the automatic gain within the analog-to-digital converter, the specifications or requirements of the LNA or baseband amplifiers may be reduced or limited.

Abstract: An analog filter (10) having a bandwidth tracking circuit includes an analog filter element (14) and a digital tracking loop (22). The digital tracking loop (22) compares a magnitude difference to a predetermined threshold to generate an error signal. The magnitude difference is determined during a closed loop bandwidth calibration by subtracting a first magnitude of an analog input signal over a predetermined frequency range to a second magnitude of the analog input signal over the predetermined frequency range located near the bandwidth frequency. Use of the digital tracking loop (22) provides a digital approach for achieving bandwidth tracking of an analog filter without the need for achieving any manufacturing process matching between the analog filter and the tracking circuit itself. The analog filter element (14) may be either a lowpass, highpass, bandpass, active or passive filter element.

Abstract: A sigma delta converter configured for DC offset correction is presented. The sigma delta modulator has integrator circuitry including an integrator input and an integrator output. An input signal received at the integrator input has an input AC voltage component and a DC offset component. Capacitors are connected to the integrator input, and a first set of switches is connected to the pair of capacitors. The first set of switches transfer a first charge to the pair of capacitors during a first phase, and a second set of switches transfer the first charge and a second charge to the integrator input.