Abstract: Processing equipment for the metallization of a plurality of semiconductor workpieces. A controlled atmospheric non-oxidizing gas region comprises at least two enclosed deposition zones, the controlled atmospheric non-oxidizing gas region is isolated from external oxidizing ambient. A temperature controller adjusts the temperature of the semiconductor workpiece in each of the at least two enclosed deposition zones. Each of the enclosed deposition zones comprising at least one spray gun for the metallization of the semiconductor workpiece. A transport system moves the semiconductor workpiece through the controlled atmospheric non-oxidizing gas region. A batch carrier plate carries the semiconductor workpiece through the controlled atmospheric non-oxidizing gas region. The controlled atmospheric non-oxidizing gas region further comprises a gas-based pre-cleaning zone.

Abstract: Solar cell array solutions including monolithic solar cell arrays and fabrication methods. A first patterned cell metallization contacts base and emitter regions of each of a plurality of solar cells having a light receiving frontside and a backside. An electrically insulating continuous backplane layer is attached to the backside of the solar cells and covers the first cell metallization of each of the solar cells. Via holes through the continuous backplane layer provide access to the first cell metallization. A second cell metallization is connected to the first cell metallization of each of the solar cells and electrically interconnects the solar cells in the array.

Abstract: A method of forming low dielectric insulation between pairs of conductive lines separated by insulating material of a level of interconnection for integrated circuits by selectively removing portions of the insulating material to create spaces for containing a gas with a dielectric constant of slightly above 1. Preferably, the insulating material is a conformal source of silicon oxide, such as tetraethylorthosilicate. The resultant method forms an insulation separating the conductive lines whose composite dielectric constant with the gas in the spaces between the insulating material is not greater than about 3 over a predetermined distance. An integrated circuit having a plurality of semiconductor devices being interconnected by conductive lines separated by insulating material and spaces containing a gas, composite dielectric constant of which is not greater than about 3 over a predetermined distance.

Abstract: A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (L.sub.eff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom.

Abstract: A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (L.sub.eff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom.

Abstract: A method of accurately determining the composition of a dielectric film in a semiconductor device by performing a compositional analysis on a film only portion of the semiconductor device.

Abstract: An improved process is provided for forming a multilayer structure (18) suitable for tape automated bonding thereto or for forming contacts. In the process, a first layer (12) of aluminum is formed on a substrate (10), a second layer (14) of a TiW alloy is formed on the first layer of aluminum, and a third layer (16) of gold is formed on the second layer of the TiW alloy, to which third layer of gold bonding is done. The improvement comprises annealing the second layer of the TiW alloy in an inert atmosphere at a temperature less than about 500.degree. C. for a period of time sufficient to form a film of an Al--TiW phase (20), believed to comprise TiAl.sub.3, at the interface between the first layer of aluminum and the second layer of the TiW alloy. The annealing is done prior to forming the third layer of gold on the second layer of the TiW alloy.

Abstract: The invention discloses an improved integrated circuit package having enhanced thermal conductivity comprising a molding or encapsulation resin having a semiconductor filler material. In a preferred embodiment, the semiconductor filler material comprises a high purity doped semiconductor to reduce alpha errors caused by alpha emisison normally caused by the use of fillers containing trace amounts of radioactive impurities and to provide enhanced thermal conductivity.