Abstract: Systems and methods for compressing data within a block of data for storage in memory and for transmission along a data path are described herein. By utilizing previously unused bits in data words, the valid data can be stored more efficiently and transmitted in fewer transfer cycles, thereby increasing the availability of the data bus to other masters. One embodiment of a system for storing and transmitting compressed data includes masters and slaves interconnected by a data bus. One of the masters is a video input interface configured to receive video data from an external video source. The video input interface is further configured to compress the video data using a compression algorithm based on the difference in color between two adjacent pixels. Another one of the masters is a video display controller configured to receive the compressed video data.

Abstract: Systems and methods for rearranging valid data within a block of data for transmission along a data path are described herein. By utilizing previously unused bits in data words, the valid data can be transmitted in fewer clock cycles, thereby increasing the availability of the data bus to other masters. An exemplary embodiment of a system for transmitting data along a data bus includes one or more masters, one or more slaves, and a data bus interconnecting the masters and slaves. One of the slaves is a memory controller configured to access data from an external memory device. The memory controller may be further configured to pack video data for transmission along the data bus. One of the masters is a video display controller configured to feed video data to an external video display. The video display controller may be further configured to receive the packed video data and unpack the packed video data for transmission to the video display.

Abstract: Systems and methods for rearranging valid data within a block of data for transmission along a data path are described herein. By utilizing previously unused bits in data words, the valid data can be transmitted in fewer clock cycles, thereby increasing the availability of the data bus to other masters. An exemplary embodiment of a system for transmitting data along a data bus includes one or more masters, one or more slaves, and a data bus interconnecting the masters and slaves. One of the slaves is a memory controller configured to access data from an external memory device. The memory controller may be further configured to pack video data for transmission along the data bus. One of the masters is a video display controller configured to feed video data to an external video display. The video display controller may be further configured to receive the packed video data and unpack the packed video data for transmission to the video display.

Abstract: Systems and methods for compressing data within a block of data for storage in memory and for transmission along a data path are described herein. By utilizing previously unused bits in data words, the valid data can be stored more efficiently and transmitted in fewer transfer cycles, thereby increasing the availability of the data bus to other masters. One embodiment of a system for storing and transmitting compressed data includes masters and slaves interconnected by a data bus. One of the masters is a video input interface configured to receive video data from an external video source. The video input interface is further configured to compress the video data using a compression algorithm based on the difference in color between two adjacent pixels. Another one of the masters is a video display controller configured to receive the compressed video data.

Abstract: Systems and methods are disclosed herein for controlling the way in which data access requests from different masters are handled. In one example, a memory controller comprises a request analyzer configured to receive a data access request via a data bus. The request analyzer is further configured to analyze the request to determine the identity of a master making the request. The memory controller also includes a buffer system configured to store data and a controller device configured to control how data is stored in the buffer system. The controller device controls data storage within the buffer system based on the identity of the master making the request. Generally, the memory controller may operate by transmitting a first data block in response to a request thereto and pre-fetching a second data block in anticipation of the second data block being requested on a next data access request.

Abstract: A pseudo-synchronous temporary storage element transports data between two system blocks with different clock systems by pseudo-synchronizing the clock edges of the two clock signals. The pseudo-synchronization circuit may be an integral part of a storage element, a separate pseudo-synchronization device, or a discrete add-on circuit to an off the shelf storage element device.