Patents by Inventor Hon-Huei Liu
Hon-Huei Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230099443Abstract: The invention provides a semiconductor structure, which comprises a substrate with at least a first transistor and a second transistor, and a capacitor structure in a dielectric layer above the substrate, wherein the capacitor structure is electrically connected with a gate of the first transistor and a drain of the second transistor.Type: ApplicationFiled: October 20, 2021Publication date: March 30, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hon-Huei Liu, Shih-Hung Tsai, Chun-Hsien Lin
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Publication number: 20230066509Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal-oxide semiconductor (MOS) transistor on a substrate, forming an interlayer dielectric (ILD) layer on the MOS transistor, forming a ferroelectric field effect transistor (FeFET) on the ILD layer, and forming a ferroelectric random access memory (FeRAM) on the ILD layer. The formation of the FeFET further includes first forming a semiconductor layer on the ILD layer, forming a gate structure on the semiconductor layer, and then forming a source/drain region adjacent to the gate structure.Type: ApplicationFiled: September 30, 2021Publication date: March 2, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hung Tsai, Hon-Huei Liu, Chun-Hsien Lin
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Publication number: 20230009982Abstract: A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a buffer layer on a substrate, forming a high velocity layer on the buffer layer, forming a medium velocity layer on the high velocity layer, forming a low velocity layer on the medium velocity layer, forming a piezoelectric layer on the low velocity layer, and forming an electrode on the piezoelectric layer. Preferably, the buffer layer includes silicon oxide, the high velocity layer includes graphene, the medium velocity layer includes silicon oxynitride, and the low velocity layer includes titanium oxide.Type: ApplicationFiled: August 4, 2021Publication date: January 12, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hon-Huei Liu, Shih-Hung Tsai, Chun-Hsien Lin
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Publication number: 20230009805Abstract: A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a first dielectric layer on a substrate, forming a piezoelectric layer on the first dielectric layer, forming a second dielectric layer on the piezoelectric layer, performing a photo-etching process to remove the second dielectric layer for forming a recess in the second dielectric layer, forming a metal layer in the recess, and then performing a planarizing process to remove the metal layer for forming an electrode in the recess.Type: ApplicationFiled: August 3, 2021Publication date: January 12, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hung Tsai, Hon-Huei Liu, Chun-Hsien Lin
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Patent number: 11450747Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.Type: GrantFiled: March 30, 2021Date of Patent: September 20, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsiao-Pang Chou, Hon-Huei Liu, Ming-Chang Lu, Chin-Fu Lin, Yu-Cheng Tung
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Patent number: 11387148Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.Type: GrantFiled: May 12, 2020Date of Patent: July 12, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
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Publication number: 20210242018Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.Type: ApplicationFiled: March 30, 2021Publication date: August 5, 2021Inventors: Hsiao-Pang Chou, Hon-Huei Liu, Ming-Chang Lu, Chin-Fu Lin, Yu-Cheng Tung
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Patent number: 11011376Abstract: The present invention discloses a semiconductor structure with an epitaxial layer and method of manufacturing the same. The semiconductor structure with the epitaxial layer includes a substrate, a blocking layer on the substrate, multiple recesses formed in the substrate, wherein the recess extends along <111> crystal faces of the substrate, and an epitaxial layer on the blocking layer, wherein the epitaxial layer is provided with a buried portion in each recess and an above-surface portion formed on the blocking layer.Type: GrantFiled: January 8, 2019Date of Patent: May 18, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsiao-Pang Chou, Hon-Huei Liu, Ming-Chang Lu, Chin-Fu Lin, Yu-Cheng Tung
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Publication number: 20200273758Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.Type: ApplicationFiled: May 12, 2020Publication date: August 27, 2020Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
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Patent number: 10692777Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.Type: GrantFiled: August 2, 2018Date of Patent: June 23, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
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Publication number: 20200194252Abstract: The present invention discloses a semiconductor structure with an epitaxial layer and method of manufacturing the same. The semiconductor structure with the epitaxial layer includes a substrate, a blocking layer on the substrate, multiple recesses formed in the substrate, wherein the recess extends along <111> crystal faces of the substrate, and an epitaxial layer on the blocking layer, wherein the epitaxial layer is provided with a buried portion in each recess and a surface portion formed on the blocking layer.Type: ApplicationFiled: January 8, 2019Publication date: June 18, 2020Inventors: Hsiao-Pang Chou, Hon-Huei Liu, Ming-Chang Lu, Chin-Fu Lin, Yu-Cheng Tung
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Patent number: 10418290Abstract: A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the substrate. Next, a second target pattern is formed on the substrate, across the first target pattern. Then, a third pattern is formed on a hard mask layer formed on the substrate, by using an electron beam apparatus, wherein two opposite edges of the third pattern are formed under an asymmetry control.Type: GrantFiled: February 2, 2017Date of Patent: September 17, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Hon-Huei Liu, Chia-Hung Lin, Yu-Cheng Tung
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Publication number: 20180342426Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.Type: ApplicationFiled: August 2, 2018Publication date: November 29, 2018Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
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Patent number: 10068808Abstract: A semiconductor device includes: a fin-shaped structure on a substrate, in which the fin-shaped structure includes a top portion and a bottom portion; a doped layer around the bottom portion of the fin-shaped structure; a first liner on the doped layer, and a second liner on the top portion and the bottom portion of the fin-shaped structure. Preferably, the first liner and the second liner are made of different material.Type: GrantFiled: October 17, 2016Date of Patent: September 4, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
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Publication number: 20180218917Abstract: A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the substrate. Next, a second target pattern is formed on the substrate, across the first target pattern. Then, a third pattern is formed on a hard mask layer formed on the substrate, by using an electron beam apparatus, wherein two opposite edges of the third pattern are formed under an asymmetry control.Type: ApplicationFiled: February 2, 2017Publication date: August 2, 2018Inventors: En-Chiuan Liou, Hon-Huei Liu, Chia-Hung Lin, Yu-Cheng Tung
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Publication number: 20170365675Abstract: A dummy pattern arrangement and a method of arranging dummy patterns are provided in the present invention. The dummy pattern arrangement includes a substrate with a dummy region, a plurality of first base dummy cells arranged spaced apart from each other along a first direction in the dummy region, and two first edge dummy cells arranged respectively at two opposite sides of the first base dummy cells along the first direction in the dummy region.Type: ApplicationFiled: June 16, 2016Publication date: December 21, 2017Inventors: Ching-Yu Chang, Ying-Chiao Wang, Hon-Huei Liu, Jyh-Shyang Jenq, Chung-Liang Chu, Yu-Ruei Chen
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Publication number: 20170062615Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first area and a second area is provided. A first doped layer containing a first type of dopant is formed on the substrate only in the first area. A second doped layer containing a second type of dopant is formed on the substrate only in the second area. An annealing step is performed to drive the first type of dopant and the second type of dopant into the substrate.Type: ApplicationFiled: August 27, 2015Publication date: March 2, 2017Inventors: Ying-Chiao Wang, Ssu-I Fu, Jyh-Shyang Jenq, Hon-Huei Liu, Yu-Hsiang Hung
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Patent number: 9583394Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, having a first fin structure and a second fin structure disposed thereon, next, a first isolation region is formed between the first fin structure and the second fin structure, a second isolation region is formed opposite the first fin structure from the first isolation region, and at least an epitaxial layer is formed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.Type: GrantFiled: October 14, 2016Date of Patent: February 28, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Wei Feng, Shih-Hung Tsai, Hon-Huei Liu, Chao-Hung Lin, Nan-Yuan Huang, Jyh-Shyang Jenq
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Publication number: 20170033019Abstract: A semiconductor device includes: a fin-shaped structure on a substrate, in which the fin-shaped structure includes a top portion and a bottom portion; a doped layer around the bottom portion of the fin-shaped structure; a first liner on the doped layer, and a second liner on the top portion and the bottom portion of the fin-shaped structure. Preferably, the first liner and the second liner are made of different material.Type: ApplicationFiled: October 17, 2016Publication date: February 2, 2017Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
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Publication number: 20170033015Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, having a first fin structure and a second fin structure disposed thereon, next, a first isolation region is formed between the first fin structure and the second fin structure, a second isolation region is formed opposite the first fin structure from the first isolation region, and at least an epitaxial layer is formed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.Type: ApplicationFiled: October 14, 2016Publication date: February 2, 2017Inventors: Li-Wei Feng, Shih-Hung Tsai, Hon-Huei Liu, Chao-Hung Lin, Nan-Yuan Huang, Jyh-Shyang Jenq