Patents by Inventor Hon-Jarn Lin
Hon-Jarn Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973502Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.Type: GrantFiled: May 1, 2023Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
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Patent number: 11961546Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.Type: GrantFiled: August 2, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
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Publication number: 20240046968Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.Type: ApplicationFiled: August 10, 2023Publication date: February 8, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
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Patent number: 11848040Abstract: A device includes first and second reference storage units, and first and second reference switches. The first reference switch outputs a first current at a first terminal thereof to the first reference storage unit. The first reference storage unit receives the first current at a first terminal thereof and generates a first signal, according to the first current, at a second terminal thereof to an average current circuit. The second reference switch outputs a second current at a first terminal thereof to the second reference storage unit. The second reference storage unit receives the second current at a first terminal thereof, and generates a second signal, according to the second current, at a second terminal thereof to the average current circuit. The first and second reference switches are coupled to a plurality of first memory cells by a first word line.Type: GrantFiled: December 22, 2021Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Fu Lee, Yu-Der Chih, Hon-Jarn Lin, Yi-Chun Shih
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Patent number: 11783870Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.Type: GrantFiled: June 17, 2022Date of Patent: October 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
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Publication number: 20230268909Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.Type: ApplicationFiled: May 1, 2023Publication date: August 24, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
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Patent number: 11641193Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.Type: GrantFiled: July 27, 2022Date of Patent: May 2, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
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Publication number: 20230127502Abstract: A memory cell includes a memory circuit and a multiplier circuit. The multiplier circuit includes an output node configured to output the output signal, a first transistor and an initialization circuit. The first transistor is coupled to the output node and the memory circuit, and is configured to receive at least the second signal. The initialization circuit is coupled to the first transistor by the output node, and is configured to initialize the multiplier circuit in response to at least a third signal or a fourth signal. The memory circuit is configured to store a first value of a first signal of a first storage node. The multiplier circuit is coupled to the memory circuit. The multiplier circuit is configured to generate an output signal in response to the first signal and a second signal. The output signal corresponds to a product of the first signal and the second signal.Type: ApplicationFiled: January 27, 2022Publication date: April 27, 2023Inventors: Hon-Jarn LIN, Chia-Fu LEE, Yi-Chun SHIH
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Publication number: 20220360254Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.Type: ApplicationFiled: July 27, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
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Patent number: 11469745Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.Type: GrantFiled: January 29, 2021Date of Patent: October 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
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Publication number: 20220319558Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.Type: ApplicationFiled: June 17, 2022Publication date: October 6, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
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Publication number: 20220247394Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.Type: ApplicationFiled: January 29, 2021Publication date: August 4, 2022Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
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Patent number: 11367468Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.Type: GrantFiled: February 26, 2021Date of Patent: June 21, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
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Publication number: 20220115051Abstract: A device includes first and second reference storage units, and first and second reference switches. The first reference switch outputs a first current at a first terminal thereof to the first reference storage unit. The first reference storage unit receives the first current at a first terminal thereof and generates a first signal, according to the first current, at a second terminal thereof to an average current circuit. The second reference switch outputs a second current at a first terminal thereof to the second reference storage unit. The second reference storage unit receives the second current at a first terminal thereof, and generates a second signal, according to the second current, at a second terminal thereof to the average current circuit. The first and second reference switches are coupled to a plurality of first memory cells by a first word line.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Fu LEE, Yu-Der CHIH, Hon-Jarn LIN, Yi-Chun SHIH
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Patent number: 11250908Abstract: A method for sensing logical states of memory cells in multiple segments in a memory device, each cell having a high- and low-resistance state, resulting in different cell current levels for the different resistance states. The method includes determining target reference current levels for the respective segments, at least two of the target reference current levels being different from each other; generating a reference current for each segment with the target reference current level for that segment; comparing the cell current level for each cell to the reference current level for the segment the cell is in; and determining the logical states of the memory cells based on the comparison.Type: GrantFiled: August 19, 2019Date of Patent: February 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Der Chih, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Ku-Feng Lin
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Patent number: 11211106Abstract: A device includes a first reference storage unit, a second reference storage unit, a first reference switch, and a second reference switch. The first reference switch includes a first terminal coupled to a first reference bit line, a second terminal coupled to the first reference storage unit, and a control terminal coupled a reference word line. The second reference switch includes a first terminal coupled to a second reference bit line, a second terminal coupled to the second reference storage unit, and a control terminal coupled the reference word line. The first reference storage unit is configured to receive a bit data through the first reference switch, and to generate a first signal having a first logic state.Type: GrantFiled: December 16, 2019Date of Patent: December 28, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Fu Lee, Yu-Der Chih, Hon-Jarn Lin, Yi-Chun Shih
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Publication number: 20210358532Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.Type: ApplicationFiled: August 2, 2021Publication date: November 18, 2021Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
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Patent number: 11081155Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.Type: GrantFiled: June 4, 2019Date of Patent: August 3, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
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Publication number: 20200118610Abstract: A device includes a first reference storage unit, a second reference storage unit, a first reference switch, and a second reference switch. The first reference switch includes a first terminal coupled to a first reference bit line, a second terminal coupled to the first reference storage unit, and a control terminal coupled a reference word line. The second reference switch includes a first terminal coupled to a second reference bit line, a second terminal coupled to the second reference storage unit, and a control terminal coupled the reference word line. The first reference storage unit is configured to receive a bit data through the first reference switch, and to generate a first signal having a first logic state.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Fu LEE, Yu-Der CHIH, Hon-Jarn LIN, Yi-Chun SHIH
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Publication number: 20200066335Abstract: A method for sensing logical states of memory cells in multiple segments in a memory device, each cell having a high- and low-resistance state, resulting in different cell current levels for the different resistance states. The method includes determining target reference current levels for the respective segments, at least two of the target reference current levels being different from each other; generating a reference current for each segment with the target reference current level for that segment; comparing the cell current level for each cell to the reference current level for the segment the cell is in; and determining the logical states of the memory cells based on the comparison.Type: ApplicationFiled: August 19, 2019Publication date: February 27, 2020Inventors: Yu-Der Chih, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Ku-Feng Lin