Abstract: A method for addressing multiple instances of a same type of slave device on a bus is provided that includes receiving a plurality of unique device addresses at each of the slave devices and overwriting a default device address in each of the slave devices with a different one of the unique device addresses.

Abstract: A circuit for a digitally operating linear-in-decibels attenuator circuit controlled using an analog control signal. The attenuator circuit includes a resistor ladder, digitally controlled switches, and a flash analog-to-digital converter. The resistive ladder includes resistances coupled in series between an input and output electrode. The resistive ladder also includes shunt resistances, each of which is coupled to a corresponding series resistance and to a corresponding digitally controlled switch that is controlled by a corresponding digital control signal. Each of the switches include a pole electrode coupled to a corresponding shunt resistance and to the input electrode, and a throw electrode coupled to the corresponding shunt resistance and to the common node for attenuating voltage from an input signal. The flash analog-to-digital converter is controlled by an analog control signal and outputs digital control signals in a thermometer code for controlling the digitally controlled switches.

Abstract: A phase-locked loop circuit is arranged for equalizing pulse removal. The phase-locked loop circuit includes a multi-phase pulse generator circuit that is arranged to provide a feedback signal and a gate signal from an output of a voltage-controlled oscillation circuit. The gate signal leads the feedback signal by approximately one-fourth of a period. Also, an equalizing pulse removal logic circuit is arranged to provide a sync gate signal from the feedback signal, the gate signal, and a sync signal. The sync gate signal is provided such that, if the sync signal includes equalizing pulses, the sync gate signal corresponds to an inactive logic level during the equalizing pulses. A phase-frequency detector of the phase-locked loop circuit is gated such that the phase-frequency detector is not changed by the sync signal if the sync gate signal corresponds to the inactive logic level.

Abstract: A PLL circuit is arranged to provide a wide capture range, and to lock the leading edge of the feedback signal with the center of the reference clock pulse. The PLL circuit includes a charge pump circuit, a loop filter circuit, a VCO circuit, a PFD circuit, a phase detector circuit, a frequency comparator circuit, and a multiplexer circuit. The frequency comparator circuit is configured to compare the frequency of the reference clock with the frequency of the feedback signal, and to provide a status signal based on the comparison. The comparison is a determination of whether the frequencies of the reference clock and the feedback signal are within a tolerance window. Further, the multiplexer circuit selects either the PFD output or the phase detector output based on the comparison. The PFD is employed to bring the frequencies of the feedback signal and the reference clock signal within the tolerance window.

Abstract: A frequency comparator circuit is configured to compare whether the frequency of two input signals are within a tolerance of each other. The frequency comparator circuit includes two counter circuits, an AND gate, and a frequency detector circuit that is configured to provide two reset signals. The two counter circuits are arranged to be clocked by a respective one of the two input signals, and further arranged to be reset by a respective one of the two reset signals. Further, the AND gate is arranged to perform an AND function on the overflow outputs of the first and second counter circuits to provide an status signal. If the status signal is high, the difference in frequency between the two input signals is less than the tolerance. If the status signal is low, the difference in frequency between the two input signals exceeds the tolerance.