Patents by Inventor Hon Kin Chiu

Hon Kin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8076995
    Abstract: An integrated digitally controlled linear-in-decibels attenuator circuit in which one or more sets of selection switches establish a desired attenuation by selectively connecting the input signal electrode to one or more corresponding resistive ladder networks connected in series, thereby providing a substantially more constant signal attenuation value over a wider frequency bandwidth. With a single resistive ladder network, attenuation control is achieved using a thermometer switching code. With multiple resistive ladder networks, coarse and fine attenuation control can be achieved using thermometer and bubble switching codes, respectively.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: December 13, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Publication number: 20100164656
    Abstract: An integrated digitally controlled linear-in-decibels attenuator circuit in which one or more sets of selection switches establish a desired attenuation by selectively connecting the input signal electrode to one or more corresponding resistive ladder networks connected in series, thereby providing a substantially more constant signal attenuation value over a wider frequency bandwidth. With a single resistive ladder network, attenuation control is achieved using a thermometer switching code. With multiple resistive ladder networks, coarse and fine attenuation control can be achieved using thermometer and bubble switching codes, respectively.
    Type: Application
    Filed: March 8, 2010
    Publication date: July 1, 2010
    Applicant: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Patent number: 7675380
    Abstract: An integrated digitally controlled linear-in-decibels attenuator circuit in which one or more sets of selection switches establish a desired attenuation by selectively connecting the input signal electrode to one or more corresponding resistive ladder networks connected in series, thereby providing a substantially more constant signal attenuation value over a wider frequency bandwidth. With a single resistive ladder network, attenuation control is achieved using a thermometer switching code. With multiple resistive ladder networks, coarse and fine attenuation control can be achieved using thermometer and bubble switching codes, respectively.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: March 9, 2010
    Assignee: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Publication number: 20090072931
    Abstract: An integrated digitally controlled linear-in-decibels attenuator circuit in which one or more sets of selection switches establish a desired attenuation by selectively connecting the input signal electrode to one or more corresponding resistive ladder networks connected in series, thereby providing a substantially more constant signal attenuation value over a wider frequency bandwidth. With a single resistive ladder network, attenuation control is achieved using a thermometer switching code. With multiple resistive ladder networks, coarse and fine attenuation control can be achieved using thermometer and bubble switching codes, respectively.
    Type: Application
    Filed: October 22, 2007
    Publication date: March 19, 2009
    Applicant: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Patent number: 7432671
    Abstract: A level-shifting inverting circuit provides a blanking signal to Grid 1 of a CRT. The circuit provides the blanking signal from a blanking logic signal according to a voltage transfer characteristic that is substantially similar to the voltage transfer characteristic of a standard CMOS inverter. Also, the level-shifting inverting circuit includes a switch circuit that includes a differential pair. The differential pair has the blanking logic signal at one input, and a bias signal at the other input. The switch circuit is coupled to a voltage divider that provides an output voltage that is pre-determined by a resistor ratio when the switch circuit is open. If the blanking logic signal is low, the switch circuit is open. Conversely, if the blanking logic signal is high, the switch circuit is closed, and sinks current from the voltage divider, causing the output voltage to correspond to a second pre-determined voltage level.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: October 7, 2008
    Assignee: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Patent number: 7279976
    Abstract: A differential amplifier circuit with a self-controlled common mode output voltage.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: October 9, 2007
    Assignee: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Patent number: 7277135
    Abstract: Video signal control circuitry for use in a video display system in which a variation in a brightness level of a video display signal causes a corresponding variation in a beam current signal, wherein such video signal control circuitry maintains a controllable video display signal brightness level at a substantially constant average value notwithstanding a variation in the incoming video signal brightness level.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: October 2, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peyman Hojabri, Hon Kin Chiu, Robert Eddy, Leonard Stencel, Wayne Harlan
  • Patent number: 7148757
    Abstract: A charge pump-based PLL dynamically controls loop gain in response to the frequency of an input signal. The loop gain is dynamically adjusted by varying the bias current of the charge pump circuit of the PLL. The bias current is varied in response to the voltage of a loop filter that is coupled to the output of the charge pump circuit. A voltage-to-current converter (“V/I converter”) converts the voltage of the loop filter to a current. The current is mirrored to a dynamic bias generator. The dynamic bias generator comprises a sample-and-hold circuit that is used to sample the mirrored current when the charge pump circuit is temporarily switched off. The sampled current level is used to adjust the level of the bias current of the charge pump circuit. The switching the charge pump off minimizes the disturbance of the loop filter voltage by the charge pump.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: December 12, 2006
    Assignee: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Patent number: 7102398
    Abstract: A circuit for horizontal deflection includes a first PLL circuit that is arranged to provide a first PLL output signal, and a second PLL circuit that is arranged to provide a second PLL output signal. A first PLL circuit is arranged to provide equalizing pulse removal. The first PLL circuit includes a gated PFD and an equalization pulse removal logic circuit. The equalization pulse removal logic circuit is arranged such that, if equalizing pulses occur in a sync signal, the gated PFD is gated during each equalizing pulse. The second PLL circuit is arranged to provide a wide capture range, and to lock a center of a pulse of the center of the feedback signal with the leading edge of the first PLL output signal. The second PLL circuit includes a frequency comparator circuit, a PFD, and a phase detector. The frequency comparator circuit is arranged to select either the PFD or the phase detector.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: September 5, 2006
    Assignee: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Patent number: 7084670
    Abstract: A gated phase-frequency detector circuit includes a phase-frequency detector and a multiplexer circuit. The phase-frequency detector is arranged to provide UP and DOWN signals responsive to a reference clock signal and a feedback signal. Further, the phase-frequency detector includes a first flip-flop that provides the UP signal, a second flip-flop that provides the DOWN signal, and a clear logic circuit. One input of the multiplexer circuit is coupled to the output of the first flip-flop, another input of the multiplexer circuit is arranged to receive a logic high signal, and an output of the multiplexer circuit is coupled to the D input of the first flip-flop. The multiplexer circuit is arranged to multiplex the logic high signal and the UP signal responsive to a reference gate signal. If the reference gate signal corresponds to an active level, logic level of the UP signal does not change.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 1, 2006
    Assignee: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Patent number: 6965264
    Abstract: The invention is directed to improving power consumption in an integrated circuit by reducing the leakage current of a plurality of MOS transistors with an adaptive back biasing circuit. Since the leakage current characteristic is often non-linear, the optimal back bias voltage (lowest leakage current) is typically identifiable at an inflection point in a graph of the leakage current characteristic versus back bias voltage. Also, depending upon the doping of the MOS transistors (N versus P type) and manufacturing variables for a particular fabrication process, the position of this inflection point can vary between individual integrated circuits that implement substantially the same arrangement of MOS transistors. Despite these issues, the inventive circuit can substantially reduce the leakage current by coupling an adjusted back bias voltage to the substrate of an Integrated Circuit.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: November 15, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Wai Cheong Chan, Hon Kin Chiu
  • Patent number: 6873670
    Abstract: A phase locked loop (PLL) system is arranged to automatically adjust the pre-scaler divide ratio. The PLL includes a phase-frequency detector circuit that compares a feedback clock signal to an input clock signal to provide UP and DOWN signals. A charge-pump circuit provides an oscillator control signal in response to UP and DOWN. A VCO produces an oscillator signal in response to the oscillator control signal. A first divider circuit provides an output clock signal in response to the oscillator signal, where an up-down counter circuit controls the divider ratio. A second divider circuit provides the feedback clock signal in response to the output clock signal. The up-down counter evaluates the output of the window comparator, which analyzes the oscillator control signal for proper operation with the VCO.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: March 29, 2005
    Assignee: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Patent number: 6815732
    Abstract: A silicon controlled rectifier, which has a substrate and an overlying epitaxial layer that is formed on the substrate, is formed in the epitaxial layer to have a number of semiconductor regions with alternating dopant conductivity types where a number of the regions extend through the epitaxial layer to the substrate.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: November 9, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Hon Kin Chiu
  • Patent number: 6670851
    Abstract: A cascode amplifier integrated circuit (IC) with frequency compensation capability that possesses a tight overall variation in transient rise and fall time, is relatively small in size and has a relatively high RC series circuit breakdown voltage. The cascode amplifier IC includes an input bias terminal configured to receive a bias voltage Vb, a power supply input terminal configured to receive a power supply voltage Vcc, an input signal terminal configured to receive an input voltage signal Vin, and an output signal terminal. The cascode amplifier IC also includes a gain stage circuit, an output buffer stage circuit and a resistance-capacitance (RC) series circuit configured to provide frequency compensation during operation of the cascode amplifier IC. The RC series circuit has a peaking bipolar transistor configured to provide a bipolar junction peaking capacitance between the output signal terminal and the gain stage circuit.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: December 30, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Peyman Hojabri, Hon Kin Chiu
  • Patent number: 6664809
    Abstract: A level shifter circuit for accepting low voltage inputs and providing high voltage outputs corresponding thereto. The level shifter circuit uses a reference voltage source configured to produce an intermediate voltage with respect to ground and a high voltage source. A first output transistor and a second output transistor are used for producing a high voltage swing output signal by using a high voltage source. Source follower transistors are used to switch on and switch off the first and second output transistors by using the intermediate voltage. The source follower transistors are configured to ensure the maximum voltage seen across the gates of the first and second output transistors is limited to a difference between the intermediate voltage and the high voltage source. A differential input buffer can be used for controlling the source follower transistors in accordance with a low voltage differential input.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: December 16, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Patent number: 6642747
    Abstract: A frequency detector circuit is arranged to detect a frequency difference between a clock signal and a reference clock signal. The frequency detector circuit includes four flip-flop circuits and a clear logic circuit. The clear logic circuit is arranged to clear selected flip-flop circuits. Two of the flip-flop circuits are arranged to detect two consecutive transitions in the clock signal without a clearing signal to provide a DOWN signal. The other two flip-flop circuits are arranged to detect two consecutive transitions in the reference clock signal without a clearing signal to provide an UP signal. The average of the UP and DOWN signals over a time interval corresponds to the difference in frequency between the clock signal and the reference clock signal. The UP and DOWN signals provide signals that may be employed by a charge pump circuit in a phase-locked-loop system to adjust the frequency of a VCO.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: November 4, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Patent number: 6573669
    Abstract: A circuit for driving a cathode ray tube (CRT) with frequency compensation. Specifically, the present invention discloses a CRT driver circuit comprising a cascode gain stage for amplifying an input voltage. A cascode push-pull output stage generates a video output signal from the input voltage at an output node. The video output signal drives a coupled CRT and corresponding CRT cathode. A biasing node within the push-pull output stage has a biasing voltage that is always higher than the output voltage of the video output signal. Electrodes of a vertical-integrated PNP transistor are adaptively coupled to the biasing node, output node, and the cascode gain stage to provide two parallel feedback paths for frequency compensation without any cathode current leakage. As such, a current detection circuit accurately measures cathode current from a CRT that is driven by the CRT driver circuit.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: June 3, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Patent number: 6538398
    Abstract: A circuit for driving a cathode ray tube (CRT) with cathode current detection. Specifically, the present invention discloses a CRT driver circuit comprising a push-pull configuration comprising upper and lower stages of darlington paired transistors. In the lower stage, a lower prestage circuit generates a video output signal in response to a video input signal that is amplified to drive a cathode electrode of a coupled CRT. In the upper stage, an upper prestage circuit of transistors drives a voltage divider for splitting a high voltage supply between the transistors in the lower prestage circuit. In both the upper and lower stages of darlington paired transistors, upper and lower output stages of transistors are electrically active only during transient periods of the video input signal. As such, a cathode current from a static test signal can be measured from an output through the lower prestage circuit.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: March 25, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Patent number: 6515552
    Abstract: An integrated circuit with a voltage-controlled oscillator that provides an oscillation signal with an unmodulated frequency that remains constant in response to reception of a bias current having a constant magnitude and with a modulated frequency that varies in response to reception of a modulation voltage. A current-to-voltage (I:V) conversion stage converts a bias clamp current to a control voltage. A voltage-to-current (V:I) conversion stage receives the control voltage and an external modulation voltage signal and generates the control current for a current-controlled oscillator (ICO). The control voltage is based upon the threshold voltage of one of the semiconductor devices forming the I:V conversion stage and is used to drive the V:I conversion stage so long as the external modulation voltage signal is substantially zero.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: February 4, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Hon Kin Chiu, Peyman Hojabri
  • Patent number: 6512340
    Abstract: One embodiment of the present invention includes a temperature sensor with current mode output utilized within a cathode ray tube (CRT)-based display system for providing thermal protection to a CRT driver. Specifically, the current mode output temperature sensor of the present embodiment is implemented with the CRT driver of the CRT display system. Furthermore, the temperature sensor has a current sink output that is connected to an Automatic Brightness Limiter (ABL) circuit of the CRT display. The current sink of the temperature sensor operates in a manner similar to an “OR gate” with the CRT anode current. As such, when the CRT driver temperature rises above a threshold temperature, the current mode output temperature sensor sinks a current and activates the ABL circuit. As a result, the video amplitude of the CRT driver is reduced and its temperature is stabilized.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: January 28, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Hon Kin Chiu