Patents by Inventor Hon-Sum P. Wong
Hon-Sum P. Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7928420Abstract: A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer.Type: GrantFiled: December 10, 2003Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: David V. Horak, Chung H. Lam, Hon-Sum P. Wong
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Patent number: 7795068Abstract: A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer.Type: GrantFiled: June 10, 2008Date of Patent: September 14, 2010Assignee: International Business Machines CorporationInventors: David V. Horak, Chung H. Lam, Hon-Sum P. Wong
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Publication number: 20080248624Abstract: A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer.Type: ApplicationFiled: June 10, 2008Publication date: October 9, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David V. Horak, Chung H. Lam, Hon-Sum P. Wong
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Patent number: 7101762Abstract: A structure and method of manufacturing a double-gate integrated circuit which includes forming a laminated structure having a channel layer and first insulating layers on each side of the channel layer, forming openings in the laminated structure, forming drain and source regions in the openings, removing portions of the laminated structure to leave a first portion of the channel layer exposed, forming a first gate dielectric layer on the channel layer, forming a first gate electrode on the first gate dielectric layer, removing portions of the laminated structure to leave a second portion of the channel layer exposed, forming a second gate dielectric layer on the channel layer, forming a second gate electrode on the second gate dielectric layer, doping the drain and source regions, using self-aligned ion implantation, wherein the first gate electrode and the second gate electrode are formed independent of each other.Type: GrantFiled: February 3, 2005Date of Patent: September 5, 2006Assignee: International Business Machines CorporationInventors: Guy M. Cohen, Hon-Sum P. Wong
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Patent number: 7057923Abstract: A storage cell that may be a memory cell, and integrated circuit (IC) chip including an array of the memory cells and a method of forming the IC. Each storage cell is formed between a top an bottom electrode. Each cell includes a phase change layer that may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) or GST layer. The cell also includes a stylus with the apex of the stylus contacting the GST layer.Type: GrantFiled: December 10, 2003Date of Patent: June 6, 2006Assignee: International Buisness Machines Corp.Inventors: Stephen S. Furkay, David V. Horak, Chung H. Lam, Hon-Sum P. Wong
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Patent number: 7005665Abstract: The present invention includes a method for forming a phase change material memory device and the phase change memory device produced therefrom. Specifically, the phase change memory device includes a semiconductor structure including a substrate having a first doped region flanked by a set of second doped regions; a phase change material positioned on the first doped region; and a conductor positioned on the phase change material, wherein when the phase change material is a first phase the semiconductor structure operates as a bipolar junction transistor, and when the phase change material is a second phase the semiconductor structure operates as a field effect transistor.Type: GrantFiled: March 18, 2004Date of Patent: February 28, 2006Assignee: International Business Machines CorporationInventors: Stephen S. Furkay, Hendrick Hamann, Jeffrey B. Johnson, Chung H. Lam, Hon-Sum P. Wong
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Patent number: 6982460Abstract: A structure and method of manufacturing a double-gate integrated circuit which includes forming a laminated structure having a channel layer and first insulating layers on each side of the channel layer, forming openings in the laminated structure, forming drain and source regions in the openings, removing portions of the laminated structure to leave a first portion of the channel layer exposed, forming a first gate dielectric layer on the channel layer, forming a first gate electrode on the first gate dielectric layer, removing portions of the laminated structure to leave a second portion of the channel layer exposed, forming a second gate dielectric layer on the channel layer, forming a second gate electrode on the second gate dielectric layer, doping the drain and source regions, using self-aligned ion implantation, wherein the first gate electrode and the second gate electrode are formed independent of each other.Type: GrantFiled: July 7, 2000Date of Patent: January 3, 2006Assignee: International Business Machines CorporationInventors: Guy M. Cohen, Hon-Sum P. Wong
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Patent number: 6967377Abstract: It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit comprising a first gate, a second gate, and source and drain regions adjacent the first and second gates, wherein the structure has a planar upper structure and the first gate, source and drain regions are silicided in a single self-aligned process (salicide).Type: GrantFiled: July 29, 2003Date of Patent: November 22, 2005Assignee: International Business Machines CorporationInventors: Guy M. Cohen, Hon-Sum P. Wong
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Patent number: 6797553Abstract: A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.Type: GrantFiled: July 24, 2002Date of Patent: September 28, 2004Assignee: International Business Machines CorporationInventors: James W Adkisson, Arne W. Ballantine, Ramachandra Divakaruni, Jeffrey B. Johnson, Erin C. Jones, Hon-Sum P. Wong
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Patent number: 6759710Abstract: A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.Type: GrantFiled: January 18, 2002Date of Patent: July 6, 2004Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Guy M. Cohen, Yuan Taur, Hon-Sum P. Wong
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Publication number: 20040023460Abstract: It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit comprising a first gate, a second gate, and source and drain regions adjacent the first and second gates, wherein the structure has a planar upper structure and the first gate, source and drain regions are silicided in a single self-aligned process (salicide).Type: ApplicationFiled: July 29, 2003Publication date: February 5, 2004Inventors: Guy M. Cohen, Hon-Sum P. Wong
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Patent number: 6642115Abstract: It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit comprising a first gate, a second gate, and source and drain regions adjacent the first and second gates, wherein the structure has a planar upper structure and the first gate, source and drain regions are silicided in a single self-aligned process (salicide).Type: GrantFiled: October 18, 2000Date of Patent: November 4, 2003Assignee: International Business Machines CorporationInventors: Guy M. Cohen, Hon-Sum P. Wong
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Publication number: 20020177279Abstract: A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.Type: ApplicationFiled: July 24, 2002Publication date: November 28, 2002Applicant: International Business Machines CorporationInventors: James W. Adkisson, Arne W. Ballantine, Ramachandra Divakaruni, Jeffrey B. Johnson, Erin C. Jones, Hon-Sum P. Wong
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Patent number: 6448590Abstract: A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.Type: GrantFiled: October 24, 2000Date of Patent: September 10, 2002Assignee: International Business Machines CorporationInventors: James W. Adkisson, Arne W. Ballantine, Ramachandra Divakaruni, Jeffrey B. Johnson, Erin C. Jones, Hon-Sum P. Wong
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Patent number: 6432829Abstract: An improved fin device used as the body of a field effect transistor (“FET”) and an improved process of making the fin device. The fin device allows for the fabrication of very small dimensioned metal-oxide semiconductor (“MOS”) FETs in the size range of micrometers to nanometers, while avoiding the typical short channel effects often associated with MOSFETs of these dimensions. Accordingly, higher density MOSFETs may be fabricated such that more devices may be placed on a single semiconductor wafer. The process of making the fin device results in an improved fully planarized device.Type: GrantFiled: March 8, 2001Date of Patent: August 13, 2002Assignee: International Business Machines CorporationInventors: K. Paul L. Muller, Edward J. Nowak, Hon-Sum P. Wong
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Publication number: 20020093053Abstract: A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.Type: ApplicationFiled: January 18, 2002Publication date: July 18, 2002Inventors: Kevin K. Chan, Guy M. Cohen, Yuan Taur, Hon-Sum P. Wong
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Patent number: 6365465Abstract: A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.Type: GrantFiled: March 19, 1999Date of Patent: April 2, 2002Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Guy M. Cohen, Yuan Taur, Hon-Sum P. Wong
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Patent number: 6333204Abstract: The present invention is a dual epi active pixel sensor cell having a p− region of dual thickness and a method of making the same. The dual epi active pixel sensor cell produces a sensor with improved noise and latch-up reduction and improved red absorption. The thin p− epi region is positioned in the logic region for improved latch-up immunity. The thick p− epi is position in the pixel region for improved red absorption.Type: GrantFiled: January 21, 1999Date of Patent: December 25, 2001Assignee: International Business Machines CorporationInventors: Terence B. Hook, Hon-Sum P. Wong
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Publication number: 20010036731Abstract: An improved fin device used as the body of a field effect transistor (“FET”) and an improved process of making the fin device. The fin device allows for the fabrication of very small dimensioned metal-oxide semiconductor (“MOS”) FETs in the size range of micrometers to nanometers, while avoiding the typical short channel effects often associated with MOSFETs of these dimensions. Accordingly, higher density MOSFETs may be fabricated such that more devices may be placed on a single semiconductor wafer. The process of making the fin device results in an improved fully planarized device.Type: ApplicationFiled: March 8, 2001Publication date: November 1, 2001Inventors: K. Paul L. Muller, Edward J. Nowak, Hon-Sum P. Wong
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Publication number: 20010036696Abstract: A method and structure for forming an integrated circuit chip having at least one opening in a substrate includes forming an opening having vertical walls in the substrate, protecting a first portion of the vertical walls of the opening, leaving a second portion of the vertical walls unprotected, and laterally patterning the second portion of the opening to change a shape or property of the opening.Type: ApplicationFiled: July 2, 2001Publication date: November 1, 2001Inventors: K. Paul Muller, Hon-Sum P. Wong