Abstract: A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation.

Abstract: A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.

Abstract: A semiconductor monolithic IC includes a semiconductor substrate having a rectangular shape in plan view, multiple chiplets each comprising a circuit, wherein the multiple chiplets are disposed over the semiconductor substrate and are separated from each other by die-to-die spaces filled with a dielectric material, and a plurality of conductive connection patterns electrically connecting the multiple chiplets so that a combination of the circuit of the multiple chiplet function as one functional circuit. The chip region has a larger area than a maximum exposure area of a lithography apparatus used to fabricate the first and second circuits.

Abstract: A magnetoresistive random access memory (MRAM) cell includes a bottom electrode, a magnetic tunnel junction structure, a bipolar tunnel junction selector; and a top electrode. The tunnel junction selector includes a MgO tunnel barrier layer and provides a bipolar function for putting the MTJ structure in parallel or anti-parallel mode.

Abstract: A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.

Abstract: A semiconductor monolithic IC includes a semiconductor substrate having a rectangular shape in plan view, multiple chiplets each comprising a circuit, wherein the multiple chiplets are disposed over the semiconductor substrate and are separated from each other by die-to-die spaces filled with a dielectric material, and a plurality of conductive connection patterns electrically connecting the multiple chiplets so that a combination of the circuit of the multiple chiplet function as one functional circuit. The chip region has a larger area than a maximum exposure area of a lithography apparatus used to fabricate the first and second circuits.

Abstract: A magnetoresistive random access memory (MRAM) cell includes a bottom electrode, a magnetic tunnel junction structure, a bipolar tunnel junction selector; and a top electrode. The tunnel junction selector includes a MgO tunnel barrier layer and provides a bipolar function for putting the MTJ structure in parallel or anti-parallel mode.

Abstract: A memory device and a memory circuit is provided. The memory device includes a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ), a read word line, a selector and a write word line. The MTJ stands on the SOT layer. The read word line is electrically connected to the MTJ. The write word line is connected to the SOT layer through the selector. The write word line is electrically connected to the SOT layer when the selector is turned on, and the write word line is electrically isolated from the SOT layer when the selector is in an off state.

Abstract: A memory structure includes a substrate. The memory structure further includes a first transistor, wherein the first transistor is a first distance from the substrate. The memory structure further includes a second transistor, wherein the second transistor is a second distance from the substrate, and the first distance is different from the second distance, and a first source/drain (S/D) region of the first transistor is connected to a second S/D region of the second transistor. The memory structure further includes a plurality of storage elements electrically connected to both the first transistor and the second transistor, wherein each of the plurality of storage elements is a third distance from the substrate, and the third distance is different from both the first distance and the second distance.

Abstract: An integrated circuit (IC) device includes a first terminal, a second terminal, a resistive memory device configured to have a first resistance level in a first state and a second resistance level in a second state, and a switching device including a control terminal and a current path. The resistive memory device and the current path are coupled in series between the first and second terminals, and the switching device is configured to, responsive to a first voltage level at the control terminal, control the current path to have a first conductance level in a first programmed state and a second conductance level in a second programmed state.

Abstract: A memory device and a memory circuit is provided. The memory device includes a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ), a read word line, a selector and a write word line. The MTJ stands on the SOT layer. The read word line is electrically connected to the MTJ. The write word line is connected to the SOT layer through the selector. The write word line is electrically connected to the SOT layer when the selector is turned on, and the write word line is electrically isolated from the SOT layer when the selector is in an off state.

Abstract: A memory device and a memory circuit is provided. The memory device includes a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ), a read word line, a selector and a write word line. The MTJ stands on the SOT layer. The read word line is electrically connected to the MTJ. The write word line is connected to the SOT layer through the selector. The write word line is electrically connected to the SOT layer when the selector is turned on, and the write word line is electrically isolated from the SOT layer when the selector is in an off state.

Abstract: A memory device and a memory circuit is provided. The memory device includes a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ), a read word line, a selector and a write word line. The MTJ stands on the SOT layer. The read word line is electrically connected to the MTJ. The write word line is connected to the SOT layer through the selector. The write word line is electrically connected to the SOT layer when the selector is turned on, and the write word line is electrically isolated from the SOT layer when the selector is in an off state.

Abstract: A magnetoresistive random access memory (MRAM) cell includes a bottom electrode, a magnetic tunnel junction structure, a bipolar tunnel junction selector; and a top electrode. The tunnel junction selector includes a MgO tunnel barrier layer and provides a bipolar function for putting the MTJ structure in parallel or anti-parallel mode.

Abstract: A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation.

Abstract: A semiconductor monolithic IC includes a semiconductor substrate having a rectangular shape in plan view, multiple chiplets each comprising a circuit, wherein the multiple chiplets are disposed over the semiconductor substrate and are separated from each other by die-to-die spaces filled with a dielectric material, and a plurality of conductive connection patterns electrically connecting the multiple chiplets so that a combination of the circuit of the multiple chiplet function as one functional circuit. The chip region has a larger area than a maximum exposure area of a lithography apparatus used to fabricate the first and second circuits.

Abstract: A magnetoresistive random access memory (MRAM) cell includes a bottom electrode, a magnetic tunnel junction structure, a bipolar tunnel junction selector; and a top electrode. The tunnel junction selector includes a MgO tunnel barrier layer and provides a bipolar function for putting the MTJ structure in parallel or anti-parallel mode.

Abstract: A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation.

Abstract: A via-level dielectric material layer is formed over a first dielectric material layer embedding a first conductive structure. A via cavity is formed through the via-level dielectric material layer. A least one straight sidewall vertically extends from a closed upper periphery of the via cavity at a top surface of the via-level dielectric material layer to a closed lower periphery of the via cavity that is adjoined to a top surface of the first conductive structure. A pillar stack structure is formed in the via cavity by sequentially forming a set of material portions containing a lower pillar structure and an upper pillar structure. The lower pillar structure and the upper pillar structure include a selector material pillar and a memory material pillar. A second conductive structure may be formed on a top surface of the pillar stack structure. The pillar stack structure may be used in an array configuration.

Abstract: A via-level dielectric material layer is formed over a first dielectric material layer embedding a first conductive structure. A via cavity is formed through the via-level dielectric material layer. A least one straight sidewall vertically extends from a closed upper periphery of the via cavity at a top surface of the via-level dielectric material layer to a closed lower periphery of the via cavity that is adjoined to a top surface of the first conductive structure. A pillar stack structure is formed in the via cavity by sequentially forming a set of material portions containing a lower pillar structure and an upper pillar structure. The lower pillar structure and the upper pillar structure include a selector material pillar and a memory material pillar. A second conductive structure may be formed on a top surface of the pillar stack structure. The pillar stack structure may be used in an array configuration.